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lithium ion battery monitoring system preliminary technical data ad7280 rev. prf information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 12-bit adc, 1us per channel conversion time 6 analog input channels, cm range 0.5v to 27.5v 6 temperature measurements inputs on chip voltage regulator cell balancing interface daisy chain interface internal reference: 3 ppm/ o c low quiescent current high input impedance serial interface with alert function 1 spi interface for up to 120 channels on chip registers for channel sequencing v dd operating range 7.5v to 30v temperature range -40 o c to 105 o c 48 lead lqfp and lfcsp packages applications lithium ion battery monitoring nickel metal hydride battery monitoring functional block diagram mux vin(6) sdin sdout vin(4) vin(3) vin(2) vin(1) vin(0) + + - - alert cs pd v dd vin(5) v ref v reg cb1 cb6 c ref agnd vss cel l balancing inter face 2.5v ref regul ator clock limit reg sqn logic d at a memo ry spi inter face contro l logic & self test ad7280 12 bit adc cnvst sdoutlo alertlo sclkhi sdinhi sdouthi alerthi cshi pdhi cnvsthi dais y chain inter face master sclk vt(6) vt(4) vt(3) vt(2) vt(1) vt(5) refgnd dgnd vdrive dvcc avcc vt term figure 1 general description the ad7280 1 contains all the functions required for general purpose monitoring of stacked lithium ion batteries as used in hybrid electric vehicles. the part has multiplexed analog input and temperature measurement channels for up to six cells of battery management. an internal 3-ppm reference is provided to drive the adc. the adc resolution is 12 bits with a 1 msps throughput rate offering a 1 s conversion time. the ad7280 operates from just one v dd supply which has a range of 7.5v to 30v (with an absolute max rating of 33v). the part provides 6 pseudo differential analog input channels to accommodate large common mode signals across the full v dd range. each channel allows an input signal range, vin(+) -- - vin(-), of 1v to 5v. the input pins assume a series stack of 6 cells. in addition the part can accommodate 6 external sensors for temperature measurement. the ad7280 includes on chip registers which allow a sequence of channel measurements to be programmed to suit the applications requirements. the ad7280 also includes an alert function which generates an interrupt output signal if the cell voltages exceed an upper or lower limit defined by the user. the ad7280 has balancing interface outputs designed to control external fet transistors to allow discharging of individual cells. the ad7280 includes a built in self test feature which internally applies a known voltage to the adc inputs. there is a daisy chain interface which allows up to 20 parts to be stacked without the need for individual device isolation. the ad7280 requires only one supply pin which takes 7ma under normal operation, while converting at 1 msps. all this functionality is provided in a 48 pin lqfp or 48 pin lfcsp package operating over a temperature range of ?40c to +105c. 1 patents pending
ad7280 preliminary technical data rev. prf | page 2 of 38 specifications v dd = 7.5 v to 30 v, v ss = 0 v, d vcc = a vcc = v reg , v drive = 2.7 v to 5.25 v, t a = -40 o c to 105 o c, unless otherwise noted table 1. parameter 1 min typ max unit test conditions/comments dc accuracy [vin(0) to vin(6)] 2 resolution 12 bits no missing codes integral nonlinearity 1 lsb differential nonlinearity 1 lsb offset error 1 lsb offset error drift 3 ppm/ o c offset error match 1 lsb gain error 1 lsb gain error drift 2 ppm/ o c gain error match 1 lsb adc unadjusted error 3,4 0.05 0.1 % -40 o c to 85 o c 0.08 0.3 % -40 o c to 105 o c total unadjusted error 5,6 0.07 0.2 % -40 o c to 85 o c 0.1 0.5 % -40 o c to 105 o c analog inputs [vin(0) to vin(6)] pseudo differential input voltage vin(n) C vin(n-1) 1v 2v ref v absolute input voltage v cm - v ref v cm + v ref v common mode input voltage 0.5 27.5 v dc leakage current 70 na cnvst pulse every 100ms input capacitance 15 pf when in track 3 pf when in hold dc accuracy [vt1 to vt6] 2 resolution 12 bits no missing codes integral nonlinearity 1 lsb differential nonlinearity 1 lsb offset error 2 lsb offset error drift 2 ppm/ o c offset error match 2 lsb gain error 2 lsb gain error drift 1.2 ppm/ o c gain error match 2 lsb adc unadjusted error 7 0.1 0.2 % -40 o c to 85 o c 0.16 0.6 % -40 o c to 105 o c total unadjusted error 8 0.15 0.4 % -40 o c to 85 o c 0.2 1 % -40 o c to 105 o c analog inputs (vt1 to vt6) input voltage range 0 2v ref v leakage current 70 na cnvst pulse every 100ms input capacitance 15 pf when in track 3 pf when in hold dynamic performance common mode rejection ratio [cmrr] -75 db up to 10khz ripple frequency
preliminary technical data ad7280 rev. prf| page 3 of 38 parameter 1 min typ max unit test conditions/comments reference reference voltage 2.495 2.5 2.505 v v ref @ 25 o c reference temperature coefficient 3 15 ppm/c -40 o c to +85 o c output voltage hysteresis 50 ppm -40 o c to +85 o c long term drift 100 ppm/1000 hours line regulation 15 ppm/v avdd =7.5v turn-on settling time 10 ms v ref = 10uf , c ref = 100nf regulator output input voltage range 7.5 30 v output voltage v reg 4.75 5 5.25 v output current 9 5 ma line regulation 0.4 mv/v load regulation 2.5 mv/ma output noise voltage 700 uv internal short protection limit 20 ma for a 10 ohm short cell balancing outputs 10 output high voltage, v oh 4 5 5.25 v for a 80pf load, i source = 40 na output low voltage, v ol 0 v cb1 output ramp up time 11 5 us for a 80pf load cb1 output ramp down time 12 50 ns for a 80pf load cb2-cb6 output ramp up time 11 350 us for a 80pf load cb2-cb6 output ramp down time 12 10 us for a 80pf load logic inputs input high voltage, v inh 2.4 v input low voltage, v inl 0.4 v input current, i in 1 a input capacitance, c in 10 pf logic outputs output high voltage, v oh v drive * 0.9 v i source = 200 a output low voltage, v ol 0.4 v i sink = 200 a floating-state leakage current 1 a floating-state output capacitance 5 pf output coding straight natural binary power requirements v dd 7.5 30 v i dd during conversion 7 10 ma v dd = 30 v i dd during data readback 5 8 ma v dd = 30 v i dd during cell balancing 4.5 6 ma v dd = 30 v i dd software powerdown 1.8 2.5 ma v dd = 30 v i dd full powerdown mode 4 a v dd = 30 v power dissipation during conversion 300 mw v dd = 30 v during data readback 240 mw v dd = 30 v during cell balancing 180 mw v dd = 30 v software powerdown 75 mw v dd = 30 v full powerdown mode 120 w v dd = 30 v
ad7280 preliminary technical data rev. prf | page 4 of 38 1 temperature range is ?40c to +105c. 2 for dc accuracy specifications, the lsb size for cell voltage measurements is (2v ref -1v)/4096, the lsb size for te mperature measurements is 2v ref /4096. 3 adc unadjusted error includes the inl of the adc and the gain and offset errors of the vin0 to vin6 input channels. 4 the conversion accuracy during cell balancing is decreased due to the activation of the cell balance circuitry. the adc unadj usted error will increase from 0.1% to 0.4% within the -40 o c to 85 o c temperature range. 5 total unadjusted error includes the inl of the adc and the gain and offset errors of the vin0 to vin6 input channels as well a s the temperature coefficient of the 2.5v reference. 6 the conversion accuracy during cell balancing is decreased due to the activation of the cell balance circuitry. the total una djusted error will increase from 0.2% to 0.8% within the -40 o c to 85 o c temperature range. 7 adc unadjusted error includes the inl of the adc and the gain and offset errors of the vt input channels. 8 total unadjusted error includes the inl of the adc and the gain and offset errors of the vt input channels as well as the temp erature coefficient of the 2.5v reference. 9 this spec outlines the regulator output current which is available for external use, that is, it do es not include the regulato r current already being used by the ad7280. 10 cb output can be set to 0v or 5v with respect to negative terminal of cell being balanced. 11 the cb1 to cb6 output ramp up times are defined from the rising edge of the cs command until the cb output exceeds 4v with res pect to negative terminal of cell being balanced. 12 the cb1 to cb6 output ramp down times ar e defined from the rising ed ge of the cs command until the cb output falls below 50mv with respect to negative terminal of cell being balanced. timing specifications v dd = 7.5 v to 30 v, v ss = 0 v, d vcc = a vcc = v reg , v drive = 2.7 v to 5.25 v, t a = -40 o c to 105 o c, unless otherwise noted. 1 table 2. limit at t min , t max parameter 2.7 v v drive < 4.75 v 4.75 v v drive 5.25 v unit test conditions/comments t conv 610 610 ns max adc conversion time t delay 200 200 ns typ 250 250 ns max propogation delay between adjacent parts on the daisy chain t wait 5 5 s min time required between the end of conversions and beginning to read back the conversion results f sclk 10 10 khz min frequency of serial read clock 1 1 mhz max t quiet 200 200 ns min minimum quiet time required between the end of serial read and the start of the next conversion t 1 400 400 ns min minimum convst low pulse t 2 10 10 ns min cs falling edge to sclk rising edge t 3 10 10 ns max delay from cs falling edge until sdo is three-state disabled t 4 5 5 ns min sdi setup time pr ior to sclk falling edge t 5 3 3 ns min sdi hold time after sclk falling edge t 6 2 20 14 ns max data access time after sclk falling edge t 7 7 7 ns min sclk to data valid hold time t 8 0.3 t sclk 0.3 t sclk ns min sclk high pulse width t 9 0.3 t sclk 0.3 t sclk ns min sclk low pulse width t 10 3 10 10 ns min cs rising edge to sclk rising edge t 11 10 10 ns max cs rising edge to sdo high impedance 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v drive ) and timed from a voltage level of 1.6 v. all timing specifications given are with a 25 pf load capacitance. 2 the time required for the output to cross 0.4 v or 2.4 v. 3 t 10 applies when using a continuous sclk.
preliminary technical data ad7280 rev. prf| page 5 of 38 absolute maximum ratings t a = 25c, unless otherwise noted table 3. parameter rating v dd to agnd ?0.3 v to +33 v v ss to agnd ?0.3 v to +0.3 v vin0 to vin5 voltage to agnd v ss ? 0.3 v to v dd + 0.3 v vin6 voltage to agnd v dd ?0.3 v to v dd + 1 v cb1 output to agnd ?0.3 v to dv cc + 0.3 v cb2 to cb6 output to agnd ?0.3 v to v dd + 0.3 v vt1 to vt6 voltage to agnd ?0.3 v to av cc + 0.3 v av cc to agnd, dgnd ?0.3 v to +7 v dv cc to av cc ?0.3 v to +0.3 v dv cc to dgnd ?0.3 v to +7 v v drive to agnd ?0.3 v to dv cc +0.3 v agnd to dgnd ?0.3 v to +0.3 v digital input voltage to dgnd ?0.3 v to v drive + 0.3v digital output voltage to gnd ?0.3 v to v drive + 0.3v operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c lqfp package ja thermal impedance 76.2c/w jc thermal impedance 17c/w lfcsp package ja thermal impedance 54c/w jc thermal impedance 15c/w pb-free temperature, soldering reflow 260(+0)c esd 2kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7280 preliminary technical data rev. prf | page 6 of 38 pin configurations and functional descriptions 48 pdhi 47 cshi 46 sclkhi 45 sdihi 44 cnvsthi 43 sdohi 42 alerthi 41 refgnd 40 vref 39 cref 38 vt1 37 vt2 35 vt4 34 vt5 33 vt6 30 avcc 31 agnd 32 vtterm 36 vt3 29 vdrive 28 alertlo 27 alert 25 sdolo 26 sdo 2 cb6 3 v in5 4 cb5 7 v in3 6 cb4 5 v in4 1 v in6 8 cb3 9 v in2 10 cb2 12 cb1 11 v in1 13 vin0 14 master 15 pd 16 vdd 17 vss 18 vreg 19 dvcc 20 dgnd 21 cs 22 sclk 23 sdi 24 cnvst pin 1 ad7280 top view 00000-000 figure 2. 13 14 15 16 17 18 19 20 21 22 23 24 vin0 master pd vdd vss vreg dvcc dgnd cs sclk sdi cnvst 48 47 46 45 44 43 42 41 40 39 38 37 pdhi cshi sclkhi sdohi cnvsthi sdihi alerthi refgnd vref cref vt1 vt2 1 2 3 4 5 6 7 8 9 10 11 12 vin6 cb6 vin5 cb5 vin4 cb4 vin3 cb3 vin2 cb2 vin1 cb1 vt4 vt5 vt6 vtterm agnd avcc vdrive alertlo alert sdo sdolo 35 vt3 36 34 33 32 31 30 29 28 27 26 25 top view pin 1 indicator 00000-000 ad7280 figure 3. table 4. pin no. mnemonic description 1, 3, 5, 7, 9, 11, 13 vin6 to vin0 analog input 0 to analog in put 6. analog input 0 should be connected to the base of the series connected battery cells. analog input 1 should be connected to th e top of cell 1, analog input 2 should be connected to the top of cell 2, etc. the analog inputs are multiplexe d into the on-chip track-and- hold allowing the potential across each cell to be measured. 2, 4, 6, 8, 10, 12 cb6 to cb1 cell balance outputs. these provide a voltage output which can be used to supply the gate drives of a cell balancing transistor network. each cb(n) output prov ides a 5v voltage output re ferenced to the absolute voltage of cell(n-1). 14 master voltage input. in an application with 2 or more ad7280s daisy chained the master pin of the ad7280 connected directly to the dsp or up should be connected to the v dd supply pin through a 10kohm resistor. the master pin on the remaining ad7280s in the appl ication should be tied to their respective v ss supply pins through 10kohm resistors. 15 pd power down input. this input is used to power down the ad7280. when acting as master the pd input is supplied from the dsp/up. when acting as a slave on the daisy chain the pd input should be connected to the pdhi output of the ad7280 immediately below it in potential in the daisy chain. 16 v dd positive power supply voltage. this is the positive suppl y voltage for the high voltage analog input structure ad7280. the supply must be greater than a minimum voltag e of 7.5 v. in an application monitoring the cell voltages of up to 6 series connected battery cells the su pply voltage may be supplied directly from the cell with the highest potential. the maximum voltage which can be applied between v dd and v ss is 30v. place 10 f and 100 nf decoupling capacitors on the v dd pin. 17 v ss negative power supply voltage. this is the negative suppl y voltage for the high voltage analog input structure of the ad7280. this input should be at th e same potential as the agnd voltage. 18 v reg analog voltage output, 5v. the internally generated v reg voltage, which provides the supply voltage for the adc core, is available on this pin fo r use external to the ad7280. place 10 f and 100 nf decoupling capacitors on the v reg pin. 19 dv cc digital supply voltage, 4.75 v to 5.25 v. the dv cc and av cc voltages should ideally be at the same potential. for best performance, it is recommended that the dv cc and av cc pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 v even on a transient basis. this supply should be decoupled to dgnd. place 100 nf decoup ling capacitors on the dv cc pin. the dv cc supply pin should be connected to the v reg output 20 dgnd digital ground. ground reference point for all digita l circuitry on the ad7280. the dgnd and agnd voltages should ideally be at the same potent ial and must not be more than 0.3 v apart, even on a transient basis.
preliminary technical data ad7280 rev. prf| page 7 of 38 21 cs chip select input. when acting as a master, that is the master pin of the ad7280 is connected to v dd , the cs input is used to frame the input an d output data on the spi. the cs input also frames th e input and output data on the daisy chain interface when the mast er input of the ad7280 is connected to v ss . 22 sclk serial clock input. when acting as ma ster the sclk input is supplied from th e dsp/up. when acting as a slave on the daisy chain this input should be connected to the sclkhi output of the ad7280 immediately below it in potential in the daisy chain. 23 sdi serial data input. data to be writte n to the on-chip registers is provided on this input and is clocked into the ad7280 on the falling edge of sclk. when acting as mast er this is the data input of the spi interface. when acting as a slave on the daisy chain this input acep ts data from the sdohi o utput of the ad7280 immediately below it in potential in the daisy chain. 24 cnvst convert start input. the conversion is initiated on the falling edge of convst. when acting as master the cnvst pulse is supplied from the dsp/up. when acting as a slave on the daisy chain this input should be connected to the cnvsthi output of the ad7280 immediately below it in potential in the daisy chain. this input can also be tied to v cc and the conversion initiated through the serial interface. 25 sdolo serial data output in daisy chain mode. when configured as a slave d evice this output should be connected to the sdihi input of the ad7280 immediately below it in potential on the daisy chain. the data from each ad7280 in the daisy chain will be passed through the sd olo outputs and sdihi inp uts of each ad7280 in the chain and supplied to the up/dsp th rough the sdo output of the master ad 7280. when configured as a master device it is recommended that this output, which is not required in slave mode, be connected to v ss either directly or through a pull-down 1kohm resistor. 26 sdo serial data output. the conversion output data or the regi ster output data is supplied to this pin as a serial data stream. the bits are clocked out on the rising edge of the sclk input, and 32 sclks are required to access the data. the data is provided msb firs t. in a daisy chain application the sdo output of the master ad7280 should be connected to the up/dsp. the sdo outputs of the re maining ad7280s in the chain should be terminated to v ss through a 1k ? resistor. the data from each ad7280 in the daisy chain will be passed through the sdolo outputs and sdihi inputs of each ad7280 in the chain and supplied to the up/dsp through the sdo output of the master ad7280. 32 sclks are required for each ad7280 in the chain to access the data. 27 alert digital output. flag to indicate over voltage, under voltage, over temper ature or under temperature. the alert output of the master ad7280 should be connected to the up/dsp. the alert outputs of the remaining ad7280s in the chain should be be terminated to v ss through a 1k ? resistor. 28 alertlo alert output in daisy chain mode. the alert signal from each ad7280 in the daisy chain will be passed through the alertlo outputs and alerthi inputs of each ad7280 in the chain and supplied to the up/dsp through the alert output of the master ad7280. when configured as a slave device this output should be connected to the alerthi input of the ad7280 immediately below it in poten tial on the daisy chain. when configured as a master device it is recommended that this output, wh ich is not required in slave mode, be connected to v ss either directly or through a pull-down 1kohm resistor. 29 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. this pin should be decoupled to dgnd. the voltage range on this pin is 2.7 v to 5.25 v and may be different to the voltage at av cc and dv cc , but should never exceed either by more than 0.3 v. 30 av cc analog supply voltage, 4.75 v to 5.25 v. this is the supply voltage for the adc core. the av cc and dv cc voltages should ideally be at the same potential. for be st performance, it is recommended that the dv cc and av cc pins be shorted together, to ensure that the voltage di fference between them never exceeds 0.3 v even on a transient basis. this supply should be decoupled to agnd. place 100 nf decoupling capacitors on the av cc pin. the av cc supply pin should be externally connected to the v reg output. 31 agnd analog ground. ground reference poi nt for all analog circuitry on the ad7280. this input should be at the same potential as the base of the series connected ba ttery cells. the agnd and dgnd voltages ideally should be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 32 vt term thermistor termination resistor input. 33 to 38 vt6 to vt1 voltage temperature inp ut from potential divider with thermistor. 39 c ref a 100 nf decoupling capacitor to refg nd should be placed on this pin. 40 v ref reference output. the on-chip reference is availble on this pin for use external to the ad7280. the nominal internal reference voltage is 2.5v, which appears at the pin. a 10 f decoupling capacitor to refgnd is recommended on this pin. 41 refgnd reference ground. this is the ground reference point for the internal bandgap re ference circuitry on the ad7280. the refgnd voltage should be at th e same potential as the agnd voltage. 42 alerthi alert input in daisy chain mode. flag to indicate over voltage, under voltage, over temperature or under temperature in daisy chain mode. the alert signal from each ad7280 in the daisy ch ain will be passed through the alertlo outputs and alerthi inputs of each ad7280 in the chain and supplied to the up/dsp through the alert output of the master ad7280. this input should be connected to the alertlo output of the ad7280 immediately above it in potential on th e daisy chain. when this pin is un used,it is recommended that it is connected to v dd through a 1kohm resistor.
ad7280 preliminary technical data rev. prf | page 8 of 38 43 sdihi serial data input in daisy chain mo de. the data from each ad7280 in th e daisy chain will be passed through the sdolo outputs and sdihi inputs of each ad7280 in the chain and suppl ied to the up/dsp through the sdo output of the master ad7280. this input should be connected to the sdolo output of the ad7280 immediately above it in potential on the daisy chain. when this pin is unused,it is recommended that it is connected to v dd through a 1kohm resistor. 44 cnvsthi conversion start output in daisy chai n mode. the convert start signal fr om the up/dsp supplied to the cnvst input of the master ad7280 is passed through each ad7280 by means of the cnvst input and the cnvsthi output. this output should be connected to the cnvst pin of the ad7280 immediately above it in potential on the daisy chain. when this pi n is unused,it is recommended that it is connected to v dd . 45 sdohi serial data output in daisy chain mode. the serial data input from th e up/dsp supplied to the sdi input of the master ad7280 is passed through each ad7280 by means of the sdi input and the sd ohi output. this output should be connected to the sdi input of the ad7280 imme diately above it in potential on the daisy chain. when this pin is unused,it is reco mmended that it is connected to v dd . 46 sclkhi serial clock output in daisy chain mode. the clock signal from the up /dsp supplied to the sclk input of the master ad7280 is passed through each ad7280 by means of the sclk input and the sclkhi output. this output should be connected to the sclk input of the ad7280 imme diately above it in potential in the daisy chain. when this pin is unused,it is reco mmended that it is connected to v dd . 47 cshi chip select output in daisy chai n mode. the chip select signal from the up/dsp supplied to the cs input of the master ad7280 is passed through each ad7280 by means of the cs input and the cshi output. this output should be connected to the cs input of the ad7280 immediately above it in potential on the daisy chain. when this pin is unused,it is reco mmended that it is connected to v dd . 48 pdhi power down output in daisy chai n mode. the power down signal fr om the up/dsp supplied to the pd input of the master ad7280 is passed through each ad7280 by means of the pd input and the pdhi output. this output should be connected to the pd pin of the ad7280 immediately above it in potential on the daisy chain. when this pin is unused,it is recommend ed that it is connected to v dd .
preliminary technical data ad7280 rev. prf| page 9 of 38 terminology differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale (a point 1 lsb below the first code transition) and full scale (a point 1 lsb above the last code transition). offset code error this applies to straight binary output coding. it is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, agnd +1 lsb for vt1 to vt6 and 1v + agnd +1 lsb for vin0 to vin6. gain error this applies to straight binary output coding. it is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is 2 v ref ? 1 lsb) after adjusting for the offset error. adc unadjusted error adc unadjusted error includes integral nonlinearity errors, offset and gain errors of the adc and measurement channel. tot a l un a dju s te d e r ror ( t u e ) this is the maximum deviation of the output code from the ideal. total unadjusted error includes integral nonlinearity errors, offset and gain errors and reference drift. offset error match this is the difference in zero code error across all 6 channels. gain error match the difference in gain error across all 6 channels. track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of a conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ? lsb. common mode rejection ration (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv sine wave applied to the common-mode voltage of the vin(n) and vin(n-1) frequency, f s , as cmrr (db) = 10 log ( pf / pf s ) where pf is the power at frequency f in the adc output, and pf s is the power at frequency f s in the adc output. power supply rejection ration (psrr) variations in power supply affect the full-scale transition but not the converters linearity. psrr is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. reference voltage temperature coefficient reference voltage temperature coefficient is derived from the maximum and minimum reference output voltage ( v ref ) measured at t min , t(25c), and t max . it is expressed in ppm/c using the following equation: 6 10 )C()25( ) C) )/( = min max ref ref ref ref tt v (v(v cppm tcv c min max where: v ref ( max ) = maximum v ref at t min , t(25c), or t max v ref ( min ) = minimum v ref at t min , t(25c), or t max v ref (25 c ) = v ref at +25c t max = +85c t min = C40c output voltage hysteresis output voltage hysteresis, or thermal hysteresis, is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either t_hys+ = +25c to t max to +25c t_hysC = +25c to t min to +25c it is expressed in ppm using the following equation: 6 10 )25( )_()25( )( ? = cv hystvcv ppmv ref ref ref hys where: v ref (25 c ) = v ref at 25c v ref (t_hys) = maximum change of v ref at t_hys+ or t_hysC.
ad7280 preliminary technical data rev. prf | page 10 of 38 theory of operation circuit information the ad7280 is a lithium ion battery monitoring chip with the ability to monitor the voltage and temperature of 6 series connected battery cells. the ad7280 also provides an interface which can be used to control transistors for cell balancing. the v dd and v ss supplies required by the ad7280 can be taken from the upper and lower voltages of the series connected battery cells. an internal v reg rail is generated from the supply voltage which provides power for the adc and the internal interface circuitry. this v reg voltage is available on an output pin for use external to the ad7280. the ad7280 consists of a high voltage input multiplexer, a low voltage input multiplexer and a 12 bit adc. the high voltage multiplexer allows up to 6 series connected lithium ion battery cells to be measured. the low voltage multiplexer allows the temperature of each cell to be measured. a single cnvst signal is required to initiate conversions on all 12 channels, that is 6 voltage and 6 temperature channels. alternatively the conversion can be initiated through the rising edge of cs on the spi interface. each conversion result is stored in a results register (see register section). on power-up, the cnvst signal is the default option, this can be changed by writing to the control register. the default sequence of conversions completed following the cnvst signal, or software convert start, is all 6 voltage channels followed by all 6 temperature channels. two further conversion sequences may be selected by the user, 6 voltage channels followed by 3 temperature channels or just 6 voltage channels. the conversion sequence may be selected by writing to the control register. each voltage and temperature measurement requires a minimum of 1us to acquire and complete a conversion. depending on the external components connected to the analog inputs of the ad7280 additional acquisition time may be required. a higher acquisition time may be selected through the control register. for increased accuracy in a noisy environment the user may also select the averaging option through the control register. this option allows the user to complete 2, 4 or 8 averages on each cell voltage and cell temperature measurement. the averaged conversion results are stored in the results registers. on power-up the default combined acquisition and conversion time will be 1us, with the averaging register set to zero, that is, a single conversion per channel. the results of the voltage and temperature conversions are read back via the 4 wire serial peripheral interface. the spi interface is also used to write to and read data from the internal registers. the ad7280 features an alert function which is triggered if the voltage conversion results or the temperature conversion results exceed the maximum and minimum voltage thresholds selected by the user. the threshold levels are selected by writing to the internal registers. the ad7280 provides 6 analog output voltages which can be used to control external transistors as part of a cell balancing circuit. each cell balance output provides a 0v or 5v voltage, with respect to the potential on base of each individual cell, which can be applied to the gate of the external cell balancing transistors. the ad7280 features a daisy chain interface. individual ad7280s can monitor the cell voltages and temperatures of 6 cells, a chain of ad7280s can be used to monitor the cell voltages and temperatures of a larger number of cells. the conversion data from each ad7280 in the chain passes to the system controller via a single standard serial interface. control data can similarly be passed via the standard serial interface up the chain to each individual ad7280s the ad7280 includes an on-chip 2.5v reference. the reference voltage is available for use external to the ad7280. converter operation the ad7280 consists of a high voltage input multiplexer, a low voltage input multiplexer and a 12 bit adc. the high voltage multiplexer selects which pair of analog inputs, vin0 to vin6, are to be converted. the voltage of each individual cell is measured by converting the difference between adjacent analog inputs, that is, vin1 C vin0, vin2 C vin1, etc. this is illustrated in figure 4 and figure 5. the conversion results for each cell may be accessed after the programmed conversion sequence is complete. the second multiplexer selects which voltage temperature input, vt1 to vt6, is to be converted. the conversion results for each cell may be accessed after the programmed conversion sequence is complete. vin0 vin1 vin2 vin3 vin4 vin5 vin6 adc vin+ a d c v i n - figure 4. mux configuratio n during vin1-vin0 sampling
preliminary technical data ad7280 rev. prf| page 11 of 38 vin0 vin1 vin2 vin3 vin4 vin5 vin6 adc vin+ a d c v i n - figure 5. mux configuratio n during vin2-vin1 sampling the adc is a 12-bit successive approximation analog-to-digital converter. the converter is composed of a comparator, sar, some control logic and 2 capacitive dacs. figure 6 shows a simplified schematic of the converter. during the acquisition phase switches sw1, sw2 and sw3 are closed. the sampling capacitor array acquires the signal on the input during this phase. capacitive dac control logic capacitive dac comparator sw3 sw1 a b c s c s v in + sw2 a b v in ? figure 6. adc configuratio n during acquisition phase when the adc starts a conversion (figure 7), sw3 opens and sw1 and sw2 move to position b, causing the comparator to become unbalanced. the control logic and capacitive dacs are used to add and subtract fixed amounts of charge to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. this output code is then stored in the appropriate register for the input that has been converted. capacitive dac control logic capacitive dac comparator sw3 sw1 a b c s c s v in + sw2 a b v in ? figure 7. adc configuration during conversion phase analog input structure figure 8 shows the equivalent circuit of the analog input structure of the ad7280. the two diodes provide esd protection. the resistors are lumped components made up of the on-resistance of the input multiplexer and the track-and- hold switch. the value of these resistors is typically about 300?. capacitor c1 can primarily be attributed to pin capacitance while capacitor c2 is the sampling capacitor of the adc. the total lumped capacitance of c1 and c2 is approxi- mately 13 pf. d d v dd c2 r1 v in + v ss c1 d d v dd c2 r1 v in ? v ss c1 04852-024 figure 8. equivalent analog input circuit transfer function the output coding of the ad7280 is straight binary. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsb, and so on). the lsb size is dependent on whether the voltage or temperature inputs are being measured. the analog input range of the voltage inputs is 1v to 5v, the analog input range of the temperature inputs is 0v to 5v. the ideal transfer characteristic is shown in figure 9. table 5. lsb sizes for each analog input range selected inputs input range full-scale range lsb size voltage 1 v to 5 v 4 v/4096 976 v temperature 0 v to 5 v 5 v/4096 1.22 mv 111...111 111...110 111...000 011...111 1v + 1lsb agnd + 1lsb 5v ? 1lsb 4v input range 5v ? 1lsb 5v input range analog input adc code 000...010 000...001 000...000 04852-022 figure 9. transfer characteristic typical connection diagrams
ad7280 preliminary technical data rev pre | page 12 of 38 10f 0.1f vin0 vin1 vin2 vin3 vin4 vin5 v ss vin6vin6 c/p 4 wire spi interface optional interface pins cb6cb6 cb5 cb4 cb3 cb2 cb1 vreg master avcc dvcc vdrive vd d sclk sdi sdo alert cs pd cnvst ad7280 10uf 0.1uf 0.1uf cref vref 0.1uf 10uf 10k ? figure 10. ad7280 configuration diagram for 6 battery cells the ad7280 can be used to monitor 6 battery cells connected in series. a typical configuration for a 6 cell battery monitoring application is shown in figure 10. lithium ion battery applications require a significant number of individual cells to provide the required output voltage. individual ad7280s can monitor the cell voltages and temperatures of 6 series connected cells. the daisy chain interface of the ad7280 allows each individual ad7280 to communicate with another ad7280 immediately above or below it. the daisy chain interface allows the ad7280s to be electrically connected to the battery management chip, as shown in figure 11 without the need for individual isolation between each ad7280. daisy chain connection diagram as shown in figure 11 external diodes have been included on the v dd supply to each ad7280 and on each daisy chain signal between adjacent ad7280s. these diodes, in combination with the 10k ? series resistors on the analog inputs, are recommended to prevent damage to the ad7280 in the event of an open circuit in the battery stack. it is also recommended that a zener diode be placed across the supplies of each ad7280 as shown in figure 11. this will prevent an over voltage across the supplies of each ad7280 during the initial connection of the daisychain of ad7280s to the battery stack. a voltage rating of 33v is suggested for this zener diode but lower values may also be used to suit the application. when using a chain of ad7280s it is also recommended that a 100kohm series resistor is placed on the pd input. this is recommended to limit current into the pd pin in the event that the up/dsp or isolators are connected before the supplies of the master ad7280. please refer to the daisy chain interface section for a more detailed description of the daisy chain interface. in an application which includes a safety mechanism, designed to open circuit the battery stack, additional isolation will be required between the ad7280 above the break point and the battery management chip. emc considerations in addition to the standard decoupling capacitors, c2n and c3n, as shown in figure 11, it is also recommended that an option for additional capacitors, c1n and c4n, be included in the circuit to increase immunity to electromagnetic interference. these capacitors, placed on either side of the v dd protection diode, would be used to decouple the v dd supply of each ad7280 with respect to system ground, that is, the ground of the master ad7280 in the daisychain. it is recommended that ferrite beads be included on the battery
preliminary technical data ad7280 rev. prf| page 13 of 38 connections to the v dd and v ss supplies. it is also recommended that pull-down resistors should be used on the alert and sdo outputs on each of the slave parts in the ad7280 daisychain. c/p ad7280 v dd sclk sdi sdo alert vin0 vin1 vin2 vin3 vin4 vin5 v ss cs vin6 sclkhi cshi v ss 0 v dd 0 v dd 0 10k ? v dd sdo alert vin0 vin1 vin2 vin3 vin4 vin5 v ss master vin6 sclk alert lo cs v dd vin0 vin1 vin2 vin3 vin4 vin5 v ss vin6 v dd n pd cnvst pdhi alerthi cnvst pd cnvsthi sd ih i sdo lo sdohi sdi vreg 4 wire spi interface optional interface pins 10uf 0.1uf sdo lo alert lo master dvcc avcc vdrive vreg dvcc avcc v dd (n-1) sdo alert master vreg 10uf dvcc avcc vdrive ad7280 ad7280 100nf 10k ? 100nf 10k ? 100nf v dd 1 v dd (n-1) 10uf 10uf 0.1uf vdrive v dd (n-1) v dd 0 0.1uf 0.1uf sclkhi cshi pdhi alerthi cnvsthi sd ih i sdohi sclk alert lo cs cnvst pd sdo lo sdi sclkhi cshi pdhi alerthi cnvsthi sd ih i sdohi 0.1uf 0.1uf 0.1uf 0.1uf 10uf 0.1uf 0.1uf 10uf 0.1uf 1k ? 1k ? 1k ? 1k ? 100k ? c1 n c2 n c3 n c4 n c1 1 c2 1 c3 1 c4 1 c1 0 c3 0 c4 0 vref cref cref vre f 10uf 0.1uf vref cref 10uf 0.1uf 10uf 0.1uf 10k ? 10k ? 10k ? figure 11. ad7280 daisy chain configuration v drive the ad7280 also has a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, in the recommended configuration the ad7280 is operated with a v cc of 5 v, however the v drive pin could be powered from a 3 v supply, allowing a large dynamic range with low voltage digital processors. reference the internal reference is temperature compensated to 2.5 v 5 mv. the reference is trimmed to provide a typical drift of 3 ppm/c. the internal reference circuitry consists of a 1.2 v band gap reference and a reference buffer. the ad7280 internal
ad7280 preliminary technical data rev. prf | page 14 of 38 reference is available at the v ref pin. the v ref pin should be decoupled to refgnd using a 10 f, or greater, ceramic capacitor. the c ref pin should be decoupled to refgnd using a 0.1 f, or greater, ceramic capacitor. the internal reference is capable of driving an external load of up to 10kohms. converting cell voltages and temperatures a conversion may be initiated on the ad7280 using either the cnvst input or the serial interface. a single cnvst signal is required to initiate conversions on all 12 channels, that is 6 voltage and 6 temperature channels. alternatively the conversion can be initiated through the rising edge of cs on the spi interface. when using the cnvst input the falling edge of cnvst places the track and hold on the voltage inputs vin6 and vin5, that is across cell 6, into hold mode and initiates the conversion. at the end of the first conversion the ad7280 generates an internal end of conversion signal. this internal eoc will select the next cell voltage inputs for measurement though the multiplexer, that is, vin5 and vin4. the track-and-hold circuit will acquire the new input voltage and a second internal convert start signal is generated which places the track-and-hold into hold mode and initiates the conversion. this process is repeated until all the selected voltage and temperature cell inputs have been converted. please refer to figure 12 and figure 13. note, once all selected conversions have been completed voltage inputs vin6 and vin5 are again selected through the multiplexer and the voltage across cell 6 is acquired in preparation for the next conversion request. by setting bits d15 and d14 in the control register the voltage and temperature cells to be converted are selected. there are four options available. table 6. voltage and temperature cell selection d15 to d14 voltage inputs temperature inputs 00 1 to 6 1 to 6 01 1 to 6 1, 3 & 5 10 1 to 6 none 11 adc self test none each voltage and temperature conversion requires a minimum of 1us to acquire and convert the cell voltage or temperature voltage input. for example, when d15 and d14 are set to zero the falling edge of cnvst will trigger a series of 12 conversions. this will require a minimum of 12 s to convert all selected measurements. if no temperature conversions are required then bits d15 and d14 would be set to 10. in this case the conversion request will trigger a series of 6 conversions, requiring a minimum of 6 s. following the completion of all requested conversions the results may be read back from either a single device or from all devices in a daisychain by use of the spi and daisychain interfaces. more information on this may be found in the serial interface and daisy chain interface sections. as shown in figure 13, a wait time, t wa i t , is required between the completion of conversions and the start of readback. this time is required to synchronise between the high speed conversion clock and the lower speed clock used for all other ad7280 operations. the maximum value of t wa i t is 5s. track-and-hold the track-and-hold on the analog input of the ad7280 allows the adc to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. following a completed conversion the ad7280 enters its tracking mode. the time required to acquire an input signal depends on how quickly the sampling capacitor is charged. this in turn will depend on the input impedance and any external components placed on the analog inputs. the default acquisition time of the ad7280 on initial power up is 400 ns. this can be increased in steps of 400ns to 1.6 us to provide flexibility in selecting external components on the analog inputs. the acquisition time is selected by writing to bits d6 and d5 in the control register. it should also be noted once the acquisition time is reconfigured 90s should be allowed before performing any conversions. this time should be allowed between writing to the control register to change the acquisition time and initiating the first conversion. in the case of conv ersions which are being initiated by the rising edge of the cs pin, this will require 2 separate write commands to the control register. the first to configure the ad7280 for the required acquisition time, the second, following a delay of 90s, to initiate the conversion on the rising edge of cs . table 7.analog input acquisition time. d6 to d5 acquisition time 00 400 ns 01 800 ns 10 1.2 s 11 1.6 s the acquisition time required is calculated using the following formula: t acq = 10 (( r source + r ) c ) where: c is the sampling capacitance, the value of the sampling capacitor, 13pf r is the resistance seen by the track-and-hold amplifier looking at the input, 300 ? . r source should include any extra source impedance on the analog input.
preliminary technical data ad7280 rev. prf| page 15 of 38 cnvst t 1 internal adc conversions volt 5 volt 4 temp 6 t convert volt 6 t convert t acq figure 12. adc conversions on the ad7280 sclk serial read operation cs cnvst internal adc conversions v 6 v 4 v 5 t 6 v 6 v 5 t 1 t wait t 5 t quiet 1 32 x no. of conversions figure 13. adc conversions & readback on the ad7280 converting cell voltages and temperatures with a chain of ad7280s the ad7280 provides a daisy chain interface which allows up to 20 parts to be stacked without the need for individual isolation. one feature of this daisychain interface is the ability to initiate conversions on all parts in the daisychain stack with a single conversion start command. the conversion can be initiated through a single cnvst pulse or through the rising edge of cs on the spi interface. the convert start command is transferred up the daisychain, from the master device, to each ad7280 in turn. the delay time between each ad7280 is t delay , as outlined in figure 14. the maximum delay between the start of conversions on the master ad7280 and the last ad7280 device in the chain can be determined by multiplying t delay by the number ofad7280s in the daisychain. the total conversion time for all cell voltage and temperature conversions can be calculated using the following equation: total c onversion time = (( t acq + t conv ) (#conversions per part) - t acq + (#parts x t delay ) where t acq is the analog input acquisition time of the ad7280 as outlined in table 7 t conv is the conversion time of the ad7280 as outlined in table 2 #conversions per part is 6, 9 or 12 as outlined in table 6. #parts is the number of ad7280s in the daisychain
ad7280 preliminary technical data rev. prf | page 16 of 38 cnvst internal adc conversions part 1 volt 5 volt 4 temp 6 t conv volt 6 internal adc conversions part 2 volt 11 volt 10 temp 12 volt 12 internal adc conversions part 3 volt 17 volt 16 temp 18 volt 18 total conversion time = ((t acq + t conv ) x #conversions per part) - t acq + (#parts x t delay ) t delay t delay t delay t delay t acq + t conv t acq + t conv t acq + t conv figure 14. adc conversions & readback on a chain of 3 ad7280s suggested external component configurations on analog inputs as outlined in the track-and Chold section the acquisition time of the ad7280 is selected by the status of bits d6 and d5 in the control register. this provides flexibility in selecting external components on the analog inputs. included below are two suggested configurations for placing external components on the analog inputs to the ad7280. combined lp filter and current limiting resistors please refer to figure 15. ad7280 vin0 vin1 vin2 vin3 vin4 vin5 vin6 10k ? 100nf 100nf 100nf 100nf 100nf 100nf 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? figure 15. external series resistance & shunt capacitance the 10k ? resistor in series with the inputs provides protection to the analog inputs in the event of an over-voltage or under- voltage on those inputs. the 100nf capacitor across the pseudo differential inputs acts as a low pass filter in conjunction with the 10k ? resistor. the cut off frequency of the low pass filter is 318hz. using these external components the default acquisition time of 400 ns may be used, which will allow a combined acquisition and conversion time of 1 s. current limiting resistors please refer to figure 16. ad7280 vin0 vin1 vin2 vin3 vin4 vin5 vin6 10k? 10k? 10k ? 10k? 10k? 10k ? 10k ? figure 16. external series resistance the 10k ? resistor in series with the inputs provides protection to the analog inputs in the event of an over-voltage or under- voltage on those inputs. using these external components an acquisition time of 1.6 s should be used, which will allow a combined acquisition and conversion time of 2.2 s. self test conversion a self-test conversion may be initiated on the ad7280 which allows the operation of the adc to be verified. the self-test conversion is completed on the internal 1.2v bandgap reference voltage. the self-test conversion may be initiated on either a single ad7280 or on all ad7280s in the battery stack
preliminary technical data ad7280 rev. prf| page 17 of 38 simultaneously. the conversion results may be read back though the read protocols defined in the register map section. the self-test conversion may also be used to verify the operation of the alert outputs as described in the alert output section. conversion averaging the ad7280 includes an option where the acquisition and conversion of each cell input may be repeated with an averaged conversion result being stored in the individual register. the averaged conversion result may then be read back through the spi interface in the same manner as a standard conversion result. the ad7280 may be programmed, through bits d10 and d9 of the control register, to complete 1, 2, 4 or 8 conversions. the default on power up is a single conversion. selection of the 2, 4, or 8 average options, through the control register, will cause the control sequence of both the high voltage and low voltages input multiplexers to be reconfigured to allow the additional acquisitions and conversions to be completed. in each case the requested number of conversions will be completed on each channel before beginning to acquire and convert on the next channel in sequence. for example, if an average of 2 conversions is requested the new sequence will be voltage channel 6, voltage channel 6, voltage channel 5, vo ltage channel 5, voltage channel 4 etc. it should also be noted once the high voltage multiplexors are reconfigured, 90s should be allowed before performing any conversions. this time should be allowed between writing to the control register to select averaging and initiating the first conversion. in the case of conversions which are being initiated by the rising edge of the cs pin, this will require 2 separate write commands to the control register. the first to configure the ad7280 for the required the required averaging, the second, following a delay of 90s, to initiate the conversion on the rising edge of cs . conversion of less than 6 voltage cells the ad7280 provides 6 input channels for battery cell voltage measurement. the ad7280 may also be used in applications which require less than 6 voltage measurements. in these applications care should be taken to ensure that the sum of the individual cell voltages will still exceed the minimum v dd supply voltage. for this reason it is recommended that the minimum number of battery cells connected to each ad7280 is 4. care should also be taken to ensure that the voltage on the vin6 inputs is always greater than or equal to the voltage on the v dd supply pin. this design requirement is in place to allow the use of a diode on the v dd supply pin of the ad7280 which provides protection in the event of an open circuit in the battery stack. even if a protection diode is not being used in the application the vin6 input voltage must be greater than or equal to the v dd supply voltage. an example of the battery connections to the ad7280 in a 4 cell battery monitoring application is shown in figure 17. regardless of how many cell measurements are required in the user application the ad7280 will acquire and convert the voltages on all 6 voltage input channels. the conversion data on all 6 channels will be supplied to the dsp/up using the spi /daisy chain interfaces. the user should then ignore the conversion data which is not required in their application. if using the alert function the user should program the alert register to ensure that the shorted out channels do not incorrectly trigger an alert output. please refer to alert output section. ad7280 vin0 vin1 vin2 vin3 vin4 vin5 vin6 100nf 100nf 100nf 100nf 10k ? 10k ? 10k ? 10k ? figure 17. typical connections for a 4 cell application cell temperature inputs the ad7280 provides 6 single ended analog inputs, vt1 to vt6, to the adc which may be used to convert the voltage output of a thermistor temperature measurement circuit. in the event that no temperature measurements are required, or that individual cell temperature measurements are not required the vt inputs may be used to convert any other 0 v to 5 v input signal. the ad7280 may be programmed to complete conversions on all 6 temperature channels, on 3 temperature channels (vt1, vt3 & vt5) or on none of the temperature input channels. the number of conversions is programmed through bits d15 and d14 of the control register. the number of conversions results supplied by the ad7280 for read back by the dsp/up is programmed through bits d13 and d12 of the control register. in an application where the alert function is being used but only one or two temperature inputs are required the ad7280 should first be programmed to complete and readback only 3 temperature conversions, by setting bits d15 and d13 of the control register to 0, and bits d14 and d12 to 1. vt channels vt5 and vt3 may be removed from the alert detection by writing to bits d1 and d0 of the alert register. please refer to alert output section.
ad7280 preliminary technical data rev. prf | page 18 of 38 thermistor termination input in the event that thermistors circuits are being used to measure each individual cell temperature the thermistors termination pin, vt term , may be used to the terminate the thermistor inputs for each cell temperature measurement. this reduces the termination resistor requirement from 6 resistors to 1. bit d3 in the control register should be set to 1 when using the vt term input. it should be noted that, due to settling time requirements, the thermistor termination resistor option should only be used when the acquisition time of the ad7280 is set to its highest value, that is, 1.6 s. the acquisition time is configured by setting bits d6 and d5 of the control register as outlined in table 7. ad7280 vt6 vt5 vt4 vt3 vt2 vt1 vtterm vreg vss rterm figure 18. typical circuit using the thermistor termination resistor in the example shown the termination resistor is placed between the source voltage and the thermistor in the thermistor circuit. the vt term input may be used to terminate the thermistor inputs to either high or low voltage of the thermistor circuit. power requirements the current consumed by the ad7280 in normal operation, that is when not in powerdown mode, is dependent on the mode in which the part is being operated. in a typical lithium ion battery monitoring application there are 3 distinct modes of operation. these can be described as follows: ? voltage and temperature conversion ? ad7280 configuration & data readback ? cell balancing the ad7280 consumes its highest level of current while converting voltage and/or temperature inputs to digital outputs. depending on the configuration of the ad7280 the conversion time can be as little as 6us. as outlined in table 1 the typical current required by the ad7280 during conversion is 7ma. when configuring the chain of ad7280s or when reading back the voltage and/or temperature conversion results from a chain of ad7280s the current required for each ad7280 is typically 4ma, as outlined in table 1. the time required to read back the voltage conversions results from 96 lithium ion cells will depend on the speed of the interface clock used, that is sclk, but it can be as low as 3.2ms. the typical current consumed by the ad7280 when the cell balancing outputs are switched on is 4.5ma. the duration of the cell balance outputs on time is defined by the user. when the ad7280 is not being used in any of the above modes of operation it is recommended that the ad7280 be powered down, as outlined below. this will significantly reduce the current draw by each ad7280 on the chain which will avoid unnecessary draining of the lithium ion cells. power down the ad7280 provides a number of powerdown options. these may be described as follows: ? full powerdown (hardware) ? software powerdown the ad7280 may be placed into full powerdown mode, which requires only 4ua max current, by taking the pd pin low. the falling edge of the pd pin will power down all analog and digital circuitry. the ad7280 includes a digital filter on the pd pin which prevents the power down being initiated by noise or glitches on the hardware pd pin. a hardware power down will not be initiated until the pd pin has been held low for approximately 150s. similarly the ad7280 will not be taken out of powerdown mode until the pd pin has been held high for approximately 5s. the ad7280 may be placed into software power down mode, which requires only 1.8ma of current by setting bit d8 in the control register through the serial interface. when the ad7280 is powered down through the serial interface the regulator, the reference and the daisy chain circuitry stay powered up but the remaining analog and digital circuitry is powered down. this is necessary to ensure that the signal to power on the part, or series of parts, is correctly received. the ad7280 offers a pd timer register which allows the user to program a set time after which the ad7280 will go into power down. this will act as a time delay between the falling edge of the pd input, or the setting of bit d8 in the control register, and the ad7280 powering down. the pd timer can be set to a value between 0 and 39 minutes, with a resolution of 75 seconds. the user should first write to the pd timer register, to define the desired delay. any subsequent falling edge on the pd input or setting of bit d8 the control register, will start the pd timer and after the programmed time will place the ad7280 into powerdown. the default value of the pd timer
preliminary technical data ad7280 rev. prf| page 19 of 38 register on power up is 0h. power up time as outlined in the power down section a full power down of the ad7280, that is, an active low on the pd input, will power down all analog and digital circuitry. the recommended power up time for the internal reference, when decoupled with a 10 f capacitor, is 10ms. it is recommended that no conversions be completed until the 10ms power up time has elapsed as it may result in inaccurate data. cell balancing outputs the ad7280 provides 6 cb outputs which can be used to drive the gate of external transistors as part of a cell balancing circuit. each cb output may be set to provide either a 0v or 5v output with respect to the absolute amplitude of the negative terminal of the battery cell which is being balanced. for example, the cb6 output will provide a 0v or 5v output with respect to the voltage on the vin5 analog input. the cb outputs are set by writing to the cell balance register. the default value of the cell balance register on power up is 0h. in an application which daisychains a number of ad7280s together it is recommended that series resistors be placed between the cb outputs of the ad7280 and the gates of the external cell balancing transistors. these are recommended to protect the ad7280s in the event that the external cell balancing transistors are damaged during the initial connection of the monitoring circuitry to the battery stack. an example of how this could occur would be a connection sequence which first provides the system ground, that is the ground supply to the master ad7280 on the daisychain, followed by a connection from any of the battery cells at a potential high enough to exceed the v gs of the cell balancing transistor, for example 40v. if these two connections are the only battery connections made in the system then this will result in 40v being applied to one of the vin pins of the ad7280, which is also connected to the source input of one of the cell balancing transistors. however, because no power has been supplied to the v dd pin of the ad7280 all the cb outputs will be 0v. this will result in a reverse voltage of 40v across the v gs of the external transistor which may damage the device. in the event that the external transistor is damaged, the ad7280 may be protected by the use of 10kohm series resistors on each of the cb output pins. consideration should also be given to the protection of these external transistors during the initial connection of the monitoring circuitry to the battery stack. vin0 vin1 vin2 vin3 vin4 vin5 vin6vin6 cb6cb6 cb5 cb4 cb3 cb2 cb1 ad7280 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? figure 19. cell balancing configuration the ad7280 offers 6 cell balance timer registers which allow the on-time of each cb output to be programmed. these are referred to as the cb timer registers. the cb timers can be set to a value between 0 and 39 minutes. the resolution of the cb timer is 75 seconds. at the end of the programmed cb time the 6 cb outputs will return to their default state of 0v. the default value of the cb timer registers on power up is 0h. as noted in the power down section a power down timer may be programmed to allow cell balancing to occur for a set time before powering down the ad7280. if no power down timer has been set, that is if the pd timer register is at its default value of 0h, then a falling edge on the pd pin, or the setting of bit d8 in the control register to 1, will switch off the cb outputs and power down the ad7280. if a power down time has been set the cb outputs will be powered down when the programmed power down timer has elapsed and the ad7280 is powered down.
ad7280 preliminary technical data rev. prf | page 20 of 38 alert output the alert output on the ad7280 may be used to indicate if any of the following faults have occurred: ? over-voltage ? under-voltage ? over-temperature ? under-temperature following each completed conversion the cell voltage and temperature measurement results are compared to the fault thresholds. the fault thresholds can be set by writing to the over voltage. under voltage, over temp and under temp registers. an alert output is generated if the cell voltage or temperature results are outside the programmed fault thresholds. the alert output can be defined as a static or a dynamic output, this is set by writing to the alert register. the static alert output is a high signal which is pulled low in the event of an over or under voltage or temperature. the dynamic alert is a square wave which can be programmed to a frequency of 100hz or 1khz. the alert output may be used as part of a daisy chain in which case the ad7280 at the top of the chain, that is furthest away from the dsp/ p should be programmed to generate the initial alert output and each ad7280 in the chain will either pass that output through or pull the alert signal low to indicate that there is a fault with that particular device. at the end of the daisy chain the master ad7280, that is the ad7280 which is connected to the dsp/ p will take the alert signal from the chain and pass it, in standard digital voltage format to the dsp/ p. the functionality of the fault detection circuit, which generates the alert output, may be programmed through bits d7 to d4 of the alert register. as outlined previously (see conversion of less than 6 voltage cells) some applications may require less than 6 voltage measurements. as shown in figure 17 it is recommended that the channels which are not being used on the ad7280 be shorted to the channel below them. to prevent the incorrect triggering of the alert output in this application the ad7280 allows the user to select up to 2 voltage channels which may be taken out of the fault detection circuit. this may be programmed through bits d3 and d2 of the alert register. table 8.alert register settings d7 to d6 d5 to d4 d3 to d0 ad7280 action 00 xx xxxx no alert signal generated or passed [default] 01 xx xxxx generates static [high] alert signal to be passed down the daisy chain 10 00 xxxx generates 100hz square wave alert signal to be passed down the daisy chain 10 01 xxxx generates 1khz square wave alert signal to be passed down the daisy chain 10 10 xxxx reserved 10 11 xxxx reserved 11 xx xxxx passes alert signal from ad7280 at higher potential in daisy chain d7 to d4 d3 to d2 d1 to d0 ad7280 action xxxx 00 xx includes all 6 voltage channels in alert detection [default] xxxx 01 xx removes vin5 from alert detection xxxx 10 xx removes vin5 & vin4 from alert detection xxxx 11 xx reserved xxxx xx 00 includes all 6 temperature channels in alert detection [default] xxxx xx 01 removes vt5 from alert detection xxxx xx 10 removes vt5 & vt3 from alert detection the operation of the alert output can be verified by initiating a self-test conversion. the self-test conversion will convert a known voltage, 1.2v, which will trigger an alert output if the under voltage fault threshold is higher than 1.2v. to test the alert output the self-test should be initiated on the ad7280 furthest away from the dsp/ p. this allows the alert path through each ad7280 to be ve rified. the remaining ad7280s in the battery stack should be placed into software powerdown to ensure that only the part which is converting the self-test voltage may generate an alert output.
preliminary technical data ad7280 rev. prf| page 21 of 38 register map table 9. register name register address register data read/write register cell voltage 1 0h d11 to d0 read only cell voltage 2 1h d11 to d0 read only cell voltage 3 2h d11 to d0 read only cell voltage 4 3h d11 to d0 read only cell voltage 5 4h d11 to d0 read only cell voltage 6 5h d11 to d0 read only cell temp 1 6h d11 to d0 read only cell temp 2 7h d11 to d0 read only cell temp 3 8h d11 to d0 read only cell temp 4 9h d11 to d0 read only cell temp 5 ah d11 to d0 read only cell temp 6 bh d11 to d0 read only self test ch d11 to d0 read only control dh eh d15 to d8 d7 to d0 read/write read/write over voltage fh d7 to d0 read/write under voltage 10h d7 to d0 read/write over temp 11h d7 to d0 read/write under temp 12h d7 to d0 read/write alert 13h d7 to d0 read/write cell balance 14h d7 to d0 read/write cb timer 1 15h d7 to d0 read/write cb timer 2 16h d7 to d0 read/write cb timer 3 17h d7 to d0 read/write cb timer 4 18h d7 to d0 read/write cb timer 5 19h d7 to d0 read/write cb timer 6 1ah d7 to d0 read/write pd timer 1bh d7 to d0 read/write read 1ch d7 to d0 read/write control 3 1dh d7 to d0 read/write cell voltage registers table 10. 12-bit registers 0h to 5h d11 to d0 read/write the cell voltage registers store the conversion result from each cell input. the conversion result is in 12-bit natural binary format. cell temperature registers table 11. 12-bit register 6h to bh d11 to d0 read/write the cell temp registers store the conversion result from each temperature input. the conversion result is in 12-bit natural binary format. self-test register table 12. 12-bit register ch d11 to d0 read/write the self-test register stores the conversion result of the adc self-test. a self-test conversion is initiated by setting bits d15 and d14 of the control register to 11. the user should then pulse the cnvst input or complete a software convert start through the cs input. the conversion result is in 12-bit natural binary format. control register table 13. 16-bit register dh d15 to d8 read/write eh d7 to d0 read/write the control register is a 16-bit register that sets the ad7280 control modes. table 14. 16-bit register d15 to d14 select conversion inputs 00 = 6 voltage & 6 temp [default] 01 = 6 voltage & temp 1,3 &5 10 = 6 voltage only 11 = adc self test d13 to d12 read conversion results 00 = 6 voltage & 6 temp [default] 01 = 6 voltage & temp 1,3 &5 10 = 6 voltage only 11 = no read operation d11 conversion start format 0 = falling edge of cnvst input [default] 1 = rising edge of cs d10 to d9 conversion averaging 00 = single conversion only [default] 01 = average by 2 10 = average by 4 11 = average by 8 d8 powerdown format 0 = falling edge of pd input [default] 1 = software pd d7 software reset 0 = bring out of reset [default] 1= reset ad7280 d6 to d5 set acquisition tme 00 = acquisition time 400ns [default] 01 = acquisition time 800ns 10 = acquisition time 1.2us 11 = acquisition time 1.6us d4 reserved; set to 1 d3 thermistor termination resistor 0 = function not in use [default] 1 = termination resistor connected d2 lock device address 0 = does not lock to new device address. contiues to operate with device address 0h. [default] 1 = part locks to new devices address it is presented with.
ad7280 preliminary technical data rev. prf | page 22 of 38 d1 increment device address 0 = does not increment the device address when transferring data up the daisychain. 1 = increments the device address when transferring data up the daisychain [default] d0 daisychain register readback 0 = function not in use 1 = set daisychain for register readback [default] select conversion inputs bits d15 and d14 of the control register determine which cell voltages and temperatures are converted following a cnvst pulse or the setting of the cnvst bit, d11, in the control register. the default value of d15 and d14 on power up are 00. read conversion results bits d13 and d12 of the control register determine which cell voltages and temperatures conversion results are supplied to the serial or daisychain data outputs pins for readback. the default value of d15 and d14 on power up are 00. conversion start format the ad7280 offers two methods of initiating a conversion, the hardware cnvst pin or the software cs input. bit d11 of the control register determines whether a conversion is initiated on the falling edge of the cnvst input or on the rising edge of the cs input. the default format on power up is the cnvst pin. when using the rising edge of cs to initiate conversions it should be noted that bit d11 is reset to 0 following the initiation of conversions. conversion averaging bits d10 and d9 of the control register determines the number of conversions completed on each input with the average result being stored in the result registers. the default value of the conversion averaging bits is 00, that is, no averaging. powerdown format bit d8 of the control register allows the ad7280 be placed into a software powerdown. please refer to the power down section for more details. the default format on power up is powerdown through the pd pin. software reset bit d7 of the control register allows the user to initiate a software reset of the ad7280. two write commands are required to complete the reset operation. bit d7 must be set high to put the ad7280 into reset. bit d7 must then be set low to bring the ad7280 out of reset. select acquisition time bits d6 and d5 of the control register determine the acquisition time of the adc. please refer to the track-and- hold section for further detail. the default value of the conversion time setting is 00. table 15.analog input acquisition time. d6 to d5 acquisition time 00 400 ns 01 800 ns 10 1.2 s 11 1.6 s thermistor termination resistor bit d3 of the control register should be set if the user wishes to use a single thermistor termination resistor on the vt term pin. it should be noted that, due to settling time requirements, the thermistor termination resistor option should only be used when the acquisition time of the ad7280 is set to its highest value, that is, 1.6 s. lock devices address bit d2 of the control register is used in conjunction with bit d1 to allow individual device addresses for each ad7280 in the daisychain to be defined and locked to the part. bit d1 is used to generate the individual device addresses which are presented to each ad7280 in the daisychain in the form of a write command. when bit d2 is set high the ad7280 locks to the device address which is has been presented with. this new device address is used for all subsequent crc calculations. when bit d2 is reset low the device address of the ad7280 is not locked. in this case a device address of 0h will be used for crc calculations. increment device address bit d1 of the control register determines whether the ad7280 increments the device address it receives as part of a write command when transferring that command up the daisychain. when bit d1 is set to 1 the device address is incremented as the command is passed up the chain. this mode of operation is used on initial power up and following a reset operation to allow individual device addresses for each ad7280 in the daisychain stack to be defined, when d1 is reset to 0 no change is made to the device address as the command is passed up the chain. daisychain register readback bit d0 of the control register enables the readback of individual registers from each ad7280 is a daisychain. when bit d0 is set high the application of sufficient clocks will allow the data stored in the register address identified by the read register to be shifted out of each ad7280 in turn. this data will be passed down the daisychain and read back by the dsp/p. when bit d0 is reset low daisychain read is disabled. repeated read requests when d0 is low will result in the repeated readback of an individual register from a single device.
preliminary technical data ad7280 rev. prf| page 23 of 38 over voltage register table 16. 8-bit register fh d7 to d0 read/write the overvoltage threshold register determines the high voltage threshold of the ad7280. cell voltage conversions which exceed the over voltage threshold trigger the alert output. the ad7280 allows the user to set the over voltage threshold to a value between 1v and 5v. the resolution of the over voltage threshold is 8-bits, that is, 16mv. the default value of the over voltage threshold on power up is ffh. under voltage register table 17. 8-bit register 10h d7 to d0 read/write the under voltage threshold register determines the low voltage threshold of the ad7280. cell voltage conversions lower than the under voltage threshold trigger the alert output. the ad7280 allows the user to set the under voltage threshold to a value between 1v and 5v. the resolution of the under voltage threshold is 8-bits, that is, 16mv. the default value of the under voltage threshold on power up is 00h. over temp register table 18. 8-bit register 11h d7 to d0 read/write the over temp threshold register determines the high temperature threshold of the ad7280. cell temperature conversions which exceed the over temp threshold trigger the alert output. the ad7280 allows the user to set the over temperature threshold to a value between 0v and 5v. the resolution of the over temperature threshold is 8-bits, that is, 19mv. the default value of the over voltage threshold on power up is ffh. under temp register table 19. 8-bit register 12h d7 to d0 read/write the under temp threshold register determines the low temperature threshold of the ad7280. cell temperature conversions lower than the under voltage threshold trigger the alert output. the ad7280 allows the user to set the under temperature threshold to a value between 0v and 5v. the resolution of the under voltage threshold is 8-bits, that is, 19mv. the default value of the under voltage threshold on power up is 00h. alert register table 20. 8-bit register 13h d7 to d0 read/write the alert register determines the configuration of the alert function. the alert can be configured to be a static or dynamic signal. the static signal is a high signal which is pulled low to indicate that an over/under voltage or over/under temperature has occurred. the dynamic signal is a square wave, the frequency of which can be set to either 100hz or 1khz. when a number of ad7280s are operating in daisy chain mode the alert configuration is set on the ad7280 furthest away from the up or dsp only. the alert registers on the remaining ad7280s in the chain should be programmed to pass the alert signal through the chain. each of these parts will pass the static or dynamic alert signal through the chain or pull the signal low to indicate that an over/under voltage or over/under temperature has occurred. table 21.alert register settings d7 to d6 d5 to d4 d3 to d0 ad7280 action 00 xx xxxx no alert signal generated or passed [default] 01 xx xxxx generates static [high] alert signal to be passed down the daisy chain 10 00 xxxx generates 100hz square wave alert signal to be passed down the daisy chain 10 01 xxxx generates 1khz square wave alert signal to be passed down the daisy chain 10 10 xxxx reserved 10 11 xxxx reserved 11 xx xxxx passes alert signal from ad7280 at higher potential in daisy chain d7 to d4 d3 to d2 d1 to d0 ad7280 action xxxx 00 xx includes all 6 voltage channels in alert detection [default] xxxx 01 xx removes vin5 from alert detection xxxx 10 xx removes vin5 & vin4 from alert detection xxxx 11 xx reserved xxxx xx 00 includes all 6 temperature channels in alert detection [default] xxxx xx 01 removes vt5 from alert detection xxxx xx 10 removes vt5 & vt3 from alert detection cell balance register table 22. 8-bit register 14h d7 to d0 read/write the cell balance register determines the status of the 6 cell balance outputs. the six cb outputs are set by writing to bits d7 to d2 of the cell balance register. the default value of the cell balance register on power up is 0h. table 23. cell balance register settings d7 set cb6 output 0 = output off
ad7280 preliminary technical data rev. prf | page 24 of 38 1 = output on d6 set cb5 output 0 = output off 1 = output on d5 set cb4 output 0 = output off 1 = output on d4 set cb3 output 0 = output off 1 = output on d3 set cb3 output 0 = output off 1 = output on d2 set cb1 output 0 = output off 1 = output on d1-d0 reserved, set to 0 cb timer registers table 24. 8-bit register 15h to 1ah d7 to d0 read/write the cb timer registers allows the user to program individual on times for each of the cell balance outputs. the ad7280 allows the user to set the cb timer to a value between 0 and 39 minutes. the resolution of the cb timer is 75 seconds. the default value of the cb timer registers on power up is 0h. table 25. cb timer register settings d7-d3 5-bit binary code to set cb timer to value between 0 and 39 minutes d2-d0 reserved, set to 0 pd timer register table 26. 8-bit register 1bh d7 to d0 read/write the pd timer register determines the elapsed time before the ad7280 is automatically powered down. the ad7280 allows the user to set the pd timer to a value between 0 and 39 minutes. the resolution of the pd timer is 75 seconds. when using the pd timer in conjunction with the cb timers the value programmed to the pd timer should exceed that programmed to the cb timer by at least 1 minute. the default value of the pd timer registers on power up is 0h. table 27. pd timer register settings d7-d3 5-bit binary code to set pd timer to value between 0 and 39 minutes d2-d0 reserved, set to 0 read register table 28. 8-bit register 1ch d7 to d0 read/write the read register, in conjunction with bits d13 and d12 of the control register and bit d12 of the write operation define the read operations of the ad7280. to read back a single register from the ad7280 the register address should be first written to the read register. to read back a series of conversion results from the ad7280 an address of 0h should be written to the read register. the default value of the read register on power up is 0h. table 29. read register settings d7-d2 6-bit binary address for the register to be read d1-d0 reserved, set to 0 control 3 register table 30. 8-bit register 1dh d7 to d0 read/write the control 3 register allows the user to gate the input signal from the cnvst pin. this will hold the internal cnvst signal high regardless of any external noise or glitches on the cnvst pin. this may be used in noisy environments to prevent incorrect initiation of conversions. the default value of the control 3 register on power up is 0h. table 31. read register settings d7-d1 reserved, set to 0 d0 0 = function not in use 1 = cnvst input gated
preliminary technical data ad7280 rev. prf| page 25 of 38 serial interface the ad7280s serial interface consists of four signals; cs , sclk, sdin and sdout. the sdin line is used for transferring data into the on chip registers while the sdout line is used for reading the conversion results from the adcs. sclk is the serial clock input for the device, and all data transfers, either on sdin or on sdout, take place with respect to sclk. data is clocked into the ad7280 on the sclk falling edge. data is clocked out of the ad7280 on the sclk rising edge. the cs , input is used to frame the serial data being transferred to or from the device. cs , can also be used to initiate the sequence of conversions. figure 20 shows the timing diagram for the serial interface of the ad7280. please refer to the daisy chain interface section for further information on the daisy chain interface. writing to the ad7280 in a li-ion battery monitoring application up to 20 ad7280s may be daisy chained together to allow up to 120 individual li- ion cell voltages to be monitored. each write operation must therefore include device address and register address in addition to the data to be written. an additional identifier bit is also required when addressing all ad7280s in the daisy chain. the ad7280 spi interface, in combination with the daisy chain interface, allows any register in the 20 x ad7280 stack to be updated using one 32-bit write cycle. the 32-bit write sequence is outlined in table 32. device address the device address is a 5-bit address which allows each individual ad7280 in battery monitoring stack to be uniquely identified. on initial power up each ad7280 is configured with a default address of 0h. a simple sequence of commands, outlined in the addressing the ad7280 section, allows each ad7280 to recognize its unique in the stack. this devices address can be then locked to the ad7280 and will be used in subsequent read and write commands. the device address is written to and read from the ad7280 stack in reverse order, that is, lsb first. register address the register map for the ad7280 is outlined in table 9. each register address is 6-bit address and is used when writing to or reading from the on chip registers of the ad7280. register data when issuing a write command to a part in the stack of ad7280 devices the data to be written is an 8-bit word. as outlined in table 9, all read/write registers are 8 bits wide. more details on the correct settings for each register may be found in the register map section. address all parts the ad7280 allows write commands to be issued simultaneously to all devices on the daisychain, as well as write commands to individual ad7280s. a write to all devices on the daisychain is completed by setting the address all parts bit, d12, of the write command to 1. when issuing a write all command the device address should be set to 0h. this is also the device address to be used calculating the 8-bit crc for transmission with the write all command. 8-bit crc the ad7280 includes an 8-bit cyclic redundancy check on all write commands to either individual parts or to a chain of devices. an ad7280 which receives an invalid crc in the write command will not execute the command. the crc on the write command is calculated based on bits d31 to d11 of the write command. this includes the device address, the register address, the data to be written, the address all parts bit and bit d11. further information on the crc is outlined in cyclic redundancy check section. reading from the ad7280 there are two different types of read operation for the ad7280. ? conversion results read ? register data read the data returned from a conversion result read operation includes the device address, the channel address, a write acknowledgement bit and the 8-bit crc information in addition to the 12-bits of conver sion data. the data returned from a register data read operation includes the device address, the register address, a write acknowledgement bit and the 8-bit crc information in addition to the 8-bits of register data. the 32-bit read cycle for a conversion result read is outlined in table 33. the 32-bit read cycle for a register data read is outlined in table 34. the ad7280 spi interface, in combination with the daisy chain interface, allows the conversion results of any ad7280 in the 20 x ad7280 stack to be read back using an n x 32-bit read cycle, where n is defined by the number of conversions completed on that part, that is 12, 9 or 6 (please refer to table 6). device address the device address is a 5-bit address which allows each individual ad7280 in battery monitoring stack to be uniquely identified. on initial power up each ad7280 is configured with a default address of 0h. a simple sequence of commands, outlined in the addressing the ad7280 section, allows each ad7280 to recognize its unique in the stack. this device address can be then locked to the ad7280 and will be used in subsequent read and write commands. the device address is written to and read from the ad7280 stack in reverse order, that is, lsb first.
ad7280 preliminary technical data rev. prf | page 26 of 38 channel address the channel address allows each individual voltage and temperature result to be uniquely identified. each channel address is 4-bits wide. the addres s for each channel is detailed in the register map for the ad7280, table 9. register address the register map for the ad7280 is outlined in table 9. each register address is 6-bit address and is used when writing to or reading from the on chip registers of the ad7280. conversion data the 12-bit conversion result from the voltage inputs, the temperature inputs or the adc self-test conversion. register data the 8-bit register data which was requested in a previous write command. write acknowledgement bit as indicated above (writing to the ad7280), an 8-bit crc is included in the write command transmitted to the ad7280. this is calculated based on bits d31 to d11. a crc check is completed before the write command is executed on the device. using the same crc algorithm the ad7280 calculates the crc and compares it to that which was received by the part in the transmitted write command. if the two crc values match the command is executed and the write acknowledgment bit in the subsequent transmission of data from the device is set. if the transmitted and calculated crc do not match the write command will not be executed and the write acknowledgement bit will not be asserted, that is, it will be zero. for examples on the use of the write acknowledgment bit please refer to the write acknowledgement section. 8-bit crc the ad7280 includes an 8-bit cyclic redundancy check on all data read back from the device, that is both conversion result reads and register data reads. when reading back conversion data from the ad7280 the 8-bit crc will include the device address, the channel address, the conversion data and the write acknowledge bit. when reading back register data from the ad7280 the 8-bit crc will include the device address, the register address, the register data, two reserved zero-bits and the write acknowledge bit. in both cases the crc is generated on bits d31 to d10 of the 32-bit read cycle, and is transmitted using bits d9 to d2 of the same read cycle. further information on the crc is outlined in cyclic redundancy check section. table 32. 32-bit write cycle device address 1 register address register data address all parts reserved [zero-bit] 8-bit crc reserved [zero-bits] d31-d27 d26-d21 d20- d13 d12 d11 d10-d3 d2-d0 table 33. 32-bit read conversion result cycle device address 2 channel address conversion data write acknowledge 8-bit crc reserved [zero-bits] d31-d27 d26-d23 d22-d11 d10 d9-d2 d1-d0 table 34. 32-bit read register data cycle device address 2 register address register data zero write acknowledge 8-bit crc reserved [zero-bits] d31-d27 d26-d21 d20-d13 d12-d11 d10 d9-d2 d1-d0 1 device address should be written lsb first. for example, to address the second device on the stack, that is, the first slave d evice, the sequence of bits input to the ad7280 should be 10000. the register address, data bits and crc bits are input msb first. 2 device address is read out lsb first. the register address, channel address, all data bits and crc bits are read out msb first .
preliminary technical data ad7280 rev. prf| page 27 of 38 sdo three- state three-state cs scl k 43 2 1 23 msb-1 msb lsb t 6 t 7 t 8 t 3 t 9 t 11 sdi msb msb-1 lsb t 5 t 4 t 2 t 10 figure 20. serial interface timing diagram addressing the ad7280 in any application using a chain of ad7280s the device address corresponds to the position of the individual ad7280 in the chain with respect to the device acting as daisy chain master, that is the device connected directly to the dsp/ p. f o r example, in an application which uses 16 ad7280s to monitor 96 channels the device acting as daisy chain master should be addressed with a device address of 00000, the 16 th ad7280 in the chain should be addressed with a device address of 01111. this device address must be written to the part lsb first as outlined in table 32. on initial power up, when coming out of powerdown and following a reset operation all ad7280s in the daisychain will default to a device address of 0h. the following sequence of commands should be followed to allow each ad7280 in the daisychain to recognize its unique position in the chain. it should be noted that the following sequence will allow device addresses on all parts in the chain to be configured and confirmed through daisychain readback. a subset of these commands may also be used to simply configure the device addresses without readback confirmation. ? a single write all command should be sent to all devices in the chain to write the address of control register 2, eh, to the read register on all devices. ? a second write all command should be sent to all devices in the chain to assert the lock device address bit, d2, to de-assert the increment device address bit, d1, and to assert the daisychain register read bit, d0. ? to verify that all ad7280s in chain have received and locked their unique device address a daisychain register read should now be requested from all devices. this may be done by continuing to apply sets of 32 sclks framed by cs until the control register 2 of each device in the daisychain has been read back. the user should confirm that all device addresses are in sequence. to write to the same register on all ad7280s in the stack, bit d12, the address all bit, in the 32-bit write cycle should be set high. this will result in the 8-bit register data, bits d20-d13, being written to the same register address on all parts. the device address, bits d32-d27, should be set to 0 when writing to all parts in the stack and this device address should be used in the crc calculation, see the cyclic redundancy check section for more information. for example, when initiating a conversion using the rising edge of cs , on all ad7280s in the stack the following 32 bit write sequence must be written to the device: ? device address bits d31-d27 should be set to 0. ? register address bits d26-d21 should be set to dh to address the control register. ? register data bits d20-d13 should be set to the required settings for conversions/readback with bit d11 set to 1 in order to initiate conversions on the rising edge of cs . ? bit d12 should be set to 1 to address all parts in the stack. ? the result of the crc calculation should be filled into bits d10-d3, this will initiate a conversion on the rising edge of cs , on all ad7280s in the stack. write acknowledgement the ad7280 spi interface allows the user to write and read data to and from the ad7280 at the same time, that is, as the device is reading in one command it can provide output data on the sdout pin in the same read/write cycle. on all writes to the ad7280, the device will internally perform a crc calculation on the received data, bits d31 to d11, and it will verify this crc against that transmitted by the dsp/up. if there is a difference between the crc generated internally and that received from the dsp/up, the ad7280 will not perform the write operation. if a subsequent 32 sclk cycles framed by a cs pulse are applied to the ad7280, bit d10, the write acknowledgement bit on sdout will indicate to the processor if the last write to the device was successful (the write
ad7280 preliminary technical data rev. prf | page 28 of 38 acknowledgement bit will be set if the write was successful). the write acknowledgement bit is included in the 8-bit crc on the read cycle. an example of how this could be used when writing to and configuring a stack of ad7280 devices would be as follows; this example sets the over-voltage thresholds on all devices in the stack containing 16 ad7280s: ? execute a write all command to set register address fh (over voltage register) to the desired over voltage threshold level ? apply a further 16 sets of 32 sclks, each framed by cs to the master device ? a total of 17 sets of 32 sclk frames have now been applied to the device. the data read back from the master device on the second 32 sclk frame will include the write acknowledgement bit for the over voltage register write to the master device. the data read back from the master device on the third 32 sclk from will include the write acknowledgement bit for the over voltage register write to the first slave device in the stack and so on. it should be noted that by adding an additional step of writing to the read register on all devices in the stack first and pointing to the register being written to ensures that the data provided back from the stack of ad7280s includes this register data. in this way, the crc generated by the ad7280 and sent with the data already includes the data you have previously written to that register. cyclic redundancy check the ad7280 32-bit spi interface includes an 8-bit cyclic redundancy check (crc) on the read and write cycles. this crc may be used to detect any alteration in the data during transmission to and from the ad7280. the principle of a cyclic redundancy check is that the data to be transmitted is divided by a fixed polynomial, the remainder of this mathematical operation is then attached to the data and forms part of the transmission. at the receiving end the same mathematical operation should be completed on the data received. this will confirm that the data received is the same as the data which was originally transmitted. the polynomial used by the ad7280 to calculate the crc bits is x 8 + x 5 + x 3 + x 2 + x + 1. the division is implemented using the digital circuit outlined in figure 21. write operation crc for writes to the ad7280, the crc will need to be computed in the dsp/up and sent as part of the write command. the crc must be computed on bits d31 to d11 of the write command, that is, the device address, the register address, the data to be written, the address all parts bit and bit d11 which is a reserved zero input bit. the data is divided by the polynomial x 8 + x 5 + x 3 + x 2 + x + 1 and the 8 bit remainder, following the division, becomes the crc bits, crc[7] to crc[0]. note, if the user is addressing all parts in the stack of ad7280s (by asserting the address all parts bit d12), the crc must be computed using a device address of 0h and the data written to the device must have a device address of 0h. the ad7280 will perform the same crc calculation on bits d31 to d11 received by ad7280 and it will verify this crc against that transmitted by the dsp/up. if there is a difference between the crc generated within the ad7280 and that received from the dsp/up, the ad7280 will not perform the write operation. to allow the user to verify that the command has been received and implemented by the ad7280s in the stack, a write acknowledgement bit is also included in the 32-bit read cycles. for more information of the write acknowledgment bit, see the write acknowledgement section. read operation crc for reads from the ad7280, the 8-bit crc is generated by the ad7280 based on bits d31 to d10 of the 32 bit read cycle and is transmitted using bits d9 to d2 of the same read cycle. when reading back conversion data from the ad7280, the 8-bit crc will include the device address, the channel address, the conversion data and the write acknowledgement bit. when reading back register data from the ad7280 the 8-bit crc will include the device address, the register address, the register data, two reserved zero bits and the write acknowledgement bit. the data received is divided by the polynomial x 8 + x 5 + x 3 + x 2 + x + 1 and the 8 bit remainder, following the division, becomes the crc bits, crc[7] to crc[0]. the user can compare the crc bits calculated, with the crc that was received from the ad7280 to check if there was any al teration in the data that was transmitted by the ad7280.
preliminary technical data ad7280 rev. prf| page 29 of 38 data_in crc[0] d q d q d q d q d q d q d q d q crc[1] crc[2] crc[4] crc[3] crc[6] crc[5] crc[7] sclk figure 21. crc implementation crc pseudo code the following pseudo code may be used to calculate the crc. first, the following variables need to be declared: num_bits C the number of data bits that will be used to calculate the crc result, 21 for a data write to the ad7280 and 22 for a data read from the ad7280. i C integer variable. xor_1, xor_2, xor_3, xor_4, xor_5 C integer varibles. these are the outputs of the xor gates starting with the leftmost xor gate in the circuit implementation in figure 21. data_in C data bits that the crc will be calculated on. d31 to d11 for a write operation and d31 to d10 for a read operation. this data supplies the input to the first xor gate. crc_0, crc_1, crc_2, crc_3, crc_4, crc_5, crc_6, crc_7 C integer variables. the outputs of the shift registers starting at the leftmost shift register in the circuit implementation in figure 21. with the exception of data_in, all variables should be initialised to zero. the following code will then implement the crc calculation as outlined in figure 21 above. for (i=num_bits; i>=0; i--) { xor_5 = crc_4 ^ crc_7; xor_4 = crc_2 ^ crc_7; xor_3 = crc_1 ^ crc_7; xor_2 = crc_0 ^ crc_7; xor_1 = data_in[i] ^ crc_7; crc_7 = crc_6; crc_6 = crc_5; crc_5 = xor_5; crc_4 = crc_3; crc_3 = xor_4; crc_2 = xor_3; crc_1 = xor_2; crc_0 = xor_1; } crc calculation example 1: writing data to the high byte of the control register of device 0 in the stack, that is, the lowest device in the stack. the crc is computed in the dsp/up on bits d31 to d11, that is, the device address, the register address, the data to be written to the register, the address all parts bit and the reserved 0. device address: 00000 (5h0) register address: 001101 (6hd) data: 00001100 (8hc) address all bits: 0 (1h0) reserved 0: 0 (1h0) the data input to the crc algorithm is therefore 000000011010000110000 (21h3430). following the completion of the calculation, the value of crc_7 to crc_0 is 01010001 (8h51). the data that is sent to the ad7280 for this serial write is therefore: 0000 0001 1010 0001 1000 0010 1000 1000 (32h1a18288) crc calculation example 2: writing data to the high byte of the control register of device address 17 in the stack. the crc is computed in the dsp/up on bits d31 to d11 i.e. the device address, the register address, the data to be written to the register, the address all parts bit and the reserved 0. device address (written lsb first): 10001 (5h11) register address: 001101 (6hd) data: 00001100 (8hc) address all bits: 0 (1h0) reserved 0: 0 (1h0) the data input to the crc algorithm is therefore 100010011010000110000 (21h113430). following the completion of the calculation, the value of crc_7 to crc_0 is 10011101 (8h9d). the data that is sent to the ad7280 for this serial write is therefore: 1000 1001 1010 0001 1000 0100 1110 1000 (32h89a184e8)
ad7280 preliminary technical data rev. prf | page 30 of 38 crc calculation example 3: reading the data from the low byte of the control register of device 0 in the stack, that is, the lowest device in the stack. the crc is computed in the ad7280 on bits d31 to d10, that is, the device address, the register address, the register data, two reserved zero bits and the write acknowledgement bit. the calculated crc is sent along with bits d31 to d10 to the dsp/up. the data received from the ad7280 is as follows: 0000 0001 1100 0010 1000 0110 0110 1000 (32h1c28668) device address: 00000 (5h0) register address: 001110 (6he) register data: 00010100 (8h14) reserved 0s: 0 (2h0) write acknowledgement: 1 (1h1) crc: 10011010 (8h9a) the crc bits are computed again in the dsp/up on bits d31 to d10 of the data that is read back from the ad7280. the data input to the crc algorithm is therefore 0000000111000010100001 (22h70a1). following the completion of the calculation, the value of crc_7 to crc_0 is 10011010 (8h9a). this result matches the crc that was sent from the ad7280 so this transmission of data is valid. crc calculation example 4: reading the conversion result from channel vin3 on device 1 in the stack. the crc is computed in the ad7280 on bits d31 to d13, that is, the device address, the channel address, the conversion data, and the write acknowledgement bit. the calculated crc is sent along with bits d31 to d10 to the dsp/up. the data received from the ad7280 is as follows: 1000 0001 0100 1100 1101 0101 0001 1000 (32h814cd518) device address (read lsb first): 10000 (5h10) channel address: 0010 (4h2) conversion data: 100110011010 (12h99a) write acknowledgement: 1 (1h1) crc: 01000110 (8h46) the crc bits are computed again in the dsp/up on bits d31 to d10 of the data that is read back from the ad7280. the data input to the crc algorithm is therefore 1000000101001100110101 (22h205335). following the completion of the calculation, the value of crc_7 to crc_0 is 01000110 (8h46). this result matches the crc that was sent from the ad7280 so this transmission of data is valid.
preliminary technical data ad7280 rev. prf| page 31 of 38 daisy chain interface in a li-ion battery monitoring application up to 20 ad7280s may be daisy chained together to allow up to 120 individual li- ion cell voltages to be monitored. each ad7280 is capable of monitoring up to 6 li-ion cells and is powered from the top and bottom voltage of the 6 li-ion cells. as a result the supply voltages of each ad7280 are offset by up to 30v from adjacent ad7280s in the chain. for this reason a standard serial interface daisy chain method cannot be used. the ad7280 includes a daisy chain interface separate to the standard spi interface. this daisy chain interface allows each ad7280 in the chain to relay data to and from adjacent ad7280s. in addition to the standard 4 wire spi the ad7280 serial interface include 3 optional interface pins, alert, cnvst and pd . each input and output pin on the 7 wire interface requires at least one additional i/o for the daisy chain interface, that is, to allow the information to be passed to an ad7280 operating at a higher supply voltage. the sdo and alert outputs will also require a further daisy chain pin to allow the information to be passed to an ad7280 operating at a lower supply voltage. the remaining 5 interface pins, cs , sclk, sdi, cnvst and pd do not require additional pins to pass information to a ad7280 operating at a lower voltage as each of these input pins can operate as both spi inputs or daisy chain inputs. their functionality is defined by the state of the master pin. the master pin on the ad7280 at the base of the daisy chain should be set high, tied to v dd supply, to ensure that this device interfaces to the dsp or processor using the standard serial interface. the master pin on the remaining ad7280s in the daisy chain should each be connected to their respective v ss pins which disable the serial interface pins on those devices. this allows the cs , sclk, sdi, cnvst and pd inputs, in addition to the sdolo and alertlo outputs, to pass signals to and from an ad7280 operating at a lower potential. as explained in the serial interface section only one 32-bit write cycle is required to write to any register in the 20 x ad7280 stack. to read back the conversion data from all channels monitoring the battery stack requires only a (32 x n)-bit read cycle where n is the number of channels in the battery stack. note: this is the default read configuration on power up. if the settings of the read or control registers have been changed then additional write cycles may be required. the recommended sclk frequency to ensure correct operation of the daisy chain interface is 1mhz. with a 1mhz sclk it will take ~3.2 ms to read back the voltage conversions on 96 channels. it should be noted that when re ading from a single device in a stack of ad7280s, in some cases the sclk frequency will need to be lower than 1mhz in order to read back the register data from parts up the chain of ad7280s. this is due to the propagation delay between adjacent parts on the daisychain, see t delay in table 2. this delay does not apply if the part is reading registers or conversion data from the part in daisychain mode, that is, the max sclk of 1mhz can always be used in daisychain mode. when reading back both register and conversion data from the device using the daisychain readback mode, the sdi line must not just idle high or low but must be set up to address and write to either the top device in the chain or address and write to a part higher than the top device in the chain and set the address all parts bit to 0. a recommendation would be to write to the top available address, that is, address 31 and set the address all parts bit to 0.
ad7280 preliminary technical data rev. prf | page 32 of 38 reading data from the ad7280 there are a number of read options available on the ad7280. the user may read back the results from all the conversions completed on an individual part in the chain, from all the conversions completed on all parts in the chain or from individual registers on selected parts in the chain. in each case the user is required to first write to the read register on the selected parts to configure that part to supply the correct data on the outputs. when reading back an individual register result, the address of that register should be written to the read register of the selected part. when reading back conversion results from any or all parts in the chain an address of 0h should be written to the read register of the selected parts. when the address written to the read register is 0h the conversion results selected for read back are controlled by setting bits d13 and d12 of the control register. please refer to table 14. this allows the user to select 4 different read back options ? read back 12 conversion results: 6 voltage and 6 temperature ? read back 9 conversion results: 6 voltage and 3 temperature ? read back 6 conversion results: 6 voltage results only ? switch off read operation on this part if the user wishes to read back the conversion results from a single ad7280 in the daisy chain bits d13 and d12 of the control register on that part should be set to select the correct conversion results. bits d13 and d12 on all other ad7280s in the daisy chain should be set to switch off the read operation on those parts. it should be noted that it is more efficient in terms of 32-bit write cycles to first switch off the read operation on all ad7280s in the daisy chain. this can be achieved with a single write cycle, using bit d12 to address all parts in the chain. the user may then address the individual part and set bits d13 and d12 to select the required conversion results. when reading back conversion data from any, or all, of the ad7280s in a daisy chain the conversion results returned from the ad7280 will be the last completed set of conversions on that part. it is recommended that the user also set bits d15 and d14 of the control register, to select the number of conversions to be completed on each part, and initiate the conversions through either the cnvst pin or the rising edge of cs , as part of the read operation. this allows the user to implement a simple convert and read back routine with the most efficient number of 32-bit write and read operations. a general example of this routine, which would convert and read back from all parts in the ad7280 daisy chain would be: ? write 0h to the read register on all of the parts in the daisychain. note: 0h is the default value of this register on power up and following a reset operation. ? write to the control register on all parts. set bits d15 and d14 to select the required conversions. set bits d13 and d12 to select the required conversion results for read back. ? initiate the conversions through either the falling edge of cnvst or the rising edge of cs . ? allow sufficient time for each conversion to be completed plus 5s. please refer to converting cell voltages and temperatures section. ? apply a cs low pulse that frames 32 sclks for each conversion result to be read back. the following section outlines eleven examples of conversion and/or readback routines which would be commonly used in an application using a chain of ad7280s to monitor the voltage and/or temperature of the a stack of lithium ion batteries. example 1: convert and read all parts, all voltages and all temperatures ? register address 0h should be written to the read register on all parts. a device address of 0 is used when computing the crc for commands to write to all parts. the 32 bit write command is 32h38011c8. for a breakdown see table 35, example 1, write 1. ? bits d15-d12 of the control register should be set to 0 on all parts. the 32 bit write command is 32h1a01318. for a breakdown see table 35, example 1, write 2. ? initiate conversions through the falling edge of cnvst . ? allow sufficient time for each conversion to be completed plus 5s. following the completion of the conversions, apply a cs low pulse that frames 32 sclks for each conversion result to be read back. example 2: convert and read all parts, all voltages and three temperatures per part ? register address 0h should be written to the read register on all parts. a device address of 0 is used when computing the crc for commands to write to all parts. the 32 bit write command is 32h38011c8. for a breakdown see table 35, example 2, write 1. ? bits d15 and d13 of the control register should be set to 0, bits d14 and d12 should be set to 1 on all parts. the 32 bit write command is 32h1aa1060. for a breakdown see table 35, example 2, write 2.
preliminary technical data ad7280 rev. prf| page 33 of 38 ? initiate conversions through the falling edge of cnvst . ? allow sufficient time for each conversion to be completed plus 5s. following the completion of the conversions, apply a cs low pulse that frames 32 sclks for each conversion result to be read back. example 3: convert and read all parts, all voltages and no temperatures ? register address 0h should be written to the read register on all parts. a device address of 0 is used when computing the crc for commands to write to all parts. the 32 bit write command is 32h38011c8. for a breakdown see table 35, example 3, write 1. ? bits d15 and d13 of the control register should be set to 1, bits d14 and d12 should be set to 0 on all parts. the 32 bit write command is 32h1b415e8. for a breakdown see table 35, example 3, write 2. ? initiate conversions through the falling edge of cnvst . ? allow sufficient time for each conversion to be completed plus 5s. following the completion of the conversions, apply a cs low pulse that frames 32 sclks for each conversion result to be read back. example 4: convert and read one part, all voltages and all temperatures ? register address 0h should be written to the read register of the part that is to be read. this example uses a device address of 2. the 32 bit write command is 32h438005f0. for a breakdown see table 35, example 4, write 1. ? bits d13-d12 of the control register should be set to 1 on all parts. this switches off the read operation on all parts. the 32 bit write command is 32h1a61518. for a breakdown see table 35, example 4, write 2. ? bits d15-d12 of the control register of the part to be read from should be set to 0. this example uses a device address of 2. the 32 bit write command is 32h41a00720. for a breakdown see table 35, example 4, write 3. ? initiate conversions through the falling edge of cnvst . ? allow sufficient time for each conversion to be completed plus 5s. following the completion of the conversions, apply a cs low pulse that frames 32 sclks for each conversion result to be read back. example 5: convert and read one part, all voltages and temperatures 1, 3 & 5 ? register address 0h should be written to the read register of the part that is to be read. this example uses a device address of 5. the 32 bit write command is 32ha3800658. for a breakdown see table 35, example 5, write 1. ? bits d13-d12 of the control register should be set to 1 on all parts. this switches off the read operation on all parts. the 32 bit write command is 32h1a61518. for a breakdown see table 35, example 5, write 2. ? bit d15 and d13 of the control register of the part to be read from should be set to 0 and bits d14 and d12 should be set to 1. this example uses a device address of 5. the 32 bit write command is 32ha1aa07f0. for a breakdown see table 35, example 5, write 3. ? initiate conversions through the falling edge of cnvst . ? allow sufficient time for each conversion to be completed plus 5s. following the completion of the conversions, apply a cs low pulse that frames 32 sclks for each conversion result to be read back. example 6: convert and read one part, all voltages, no temperatures ? register address 0h should be written to the read register of the part that is to be read. this example uses a device address of 7. the 32 bit write command is 32he3800270. for a breakdown see table 35, example 6, write 1. ? bits d13-d12 of the control register should be set to 1 on all parts. this switches off the read operation on all parts. the 32 bit write command is 32h1a61518. for a breakdown see table 35, example 6, write 2. ? bits d14 and d12 of the control register of the part to be read from should be set to 0 and bits d15 and d13 should be set to 1. this example uses a device address of 7. the 32 bit write command is 32he1b40650. for a breakdown see table 35, example 6, write 3. ? initiate conversions through the falling edge of cnvst .
ad7280 preliminary technical data rev. prf | page 34 of 38 ? allow sufficient time for each conversion to be completed plus 5s. following the completion of the conversions, apply a cs low pulse that frames 32 sclks for each conversion result to be read back. example 7: convert and read a single voltage or temperature result ? the register address corresponding to the voltage or temperature result to be read should be written to the read register of the part that is to be read, see table 9 for register addresses. this example reads the cell voltage 6 result from device 3 in the stack. the 32 bit write command is 32hc3828658. for a breakdown see table 35, example 7, write 1. ? bits d13-d12 of the control register should be set to 1 on all parts. this switches off the read operation on all parts. the 32 bit write command is 32h1a61518. for a breakdown see table 35, example 7, write 2. ? bits d13 and d12 of the control register of the part to be read from should be set such that a conversion will be completed on the required channel. note: with the exception of a self-test conversion it is not possible to convert on a single channel, 6, 9 or 12 conversions must be completed. this example reads a voltage conversion from device 3 in the stack so bits d14 and d12 of the control register should be set to 0 and bits d15 and d13 should be set to 1 on device 3. the 32 bit write command is 32h c1b400f8. for a breakdown see table 35, example 7, write 3. ? initiate conversions through the falling edge of cnvst . ? allow sufficient time for each conversion to be completed plus 5s. following the completion of the conversions, apply a cs low pulse that frames 32 sclks to read back the desired voltage or temperature result. example 8: read a single configuration register all parts ? bit d0 of the control register should be set to 1 on all parts. this enables the daisychain register read operation on all parts. the 32 bit write command is 32h1c2b6e0. for a breakdown see table 35, example 8, write 1. ? the register address corresponding to the configuration register to be read should be written to the read register on all parts, see table 9 for register addresses. this example reads the cell balance register from all parts. the 32 bit write command is 32h3829348. for a breakdown see table 35, example 8, write 2. ? apply a cs low pulse that frames 32 sclks for each device in the stack to read back the desired register contents from all parts. example 9: read a single register ? bits d13-d12 of the control register should be set to 1 on all parts. this switches off the read operation on all parts. the 32 bit write command is 32h1a61518. for a breakdown see table 35, example 9, write 1. ? bits d13 and d12 of the control register of the part to be read from should be set to 0. this example reads from part 1 in the stack. the 32 bit write command is 32h81a00220. for a breakdown see table 35, example 9, write 2. ? the register address corresponding to the configuration register to be read should be written to the read register of the part that is to be read, see table 9 for register addresses. this example reads the alert register from part 1 in the stack. the 32 bit write command is 32h83898008. for a breakdown see table 35, example 9, write 3. ? apply a cs low pulse that frames 32 sclks to read back the desired register contents. example 10: self-test conversion, all parts ? bits d15-d14 of the control register should be set to 1 and bits d13-d12 should be set to 0 on all parts to select the self-test conversion. the 32 bit write command is 32h1b81090. for a breakdown see table 35, example 10, write 1. ? initiate conversions through the falling edge of cnvst . ? bit d0 of the control register should be set to 1 on all parts. this enables the daisychain register read operation on all parts. the 32 bit write command is 32h1c2b6e0. for a breakdown see table 35, example 10, write 2. ? the register address corresponding to the self-test conversion should be written to the read register of all parts, see table 9 for register addresses. the 32 bit write command is 32h38617c8. for a breakdown see table 35, example 10, write 3. ? allow sufficient time for each conversion to be
preliminary technical data ad7280 rev. prf| page 35 of 38 completed plus 5s. following the completion of the conversions, apply a cs low pulse that frames 32 sclks for each device in the stack. example 11: self-test conversion, single part ? bits d13-d12 of the control register should be set to 1 on all parts. this switches off the read operation on all parts. bit d8 in the control register of all parts should be set to 1 to put each part into a software power down. this prevents the alert function on the parts not undergoing a self-test conversion from being triggered. the 32 bit write command is 32h1a63538. for a breakdown see table 35, example 11, write 1. ? bit d8 in the control register of the part for which a self-test conversion is requested should be set to 0. this brings this part out of software power down. bits d15-d14 of the control register should be set to 1 on the part under test to select the self-test conversion. bits d13-d12 of the control register should be set to 0 the part under test to enable reads. this example reads self-test conversion result from device 4 in the stack. the 32 bit write command is 32h21b80628. for a breakdown see table 35, example 11, write 1. ? initiate conversions through the falling edge of cnvst . ? the register address corresponding to the self-test conversion should be written to the read register of the part under test (device 4 in this case); see table 9 for register addresses. the 32 bit write command is 32h23860170. for a breakdown see table 35, example 11, write 3. ? allow sufficient time the self-test conversion to be completed plus 5s. following the completion of the conversion, apply a cs low pulse that frames 32 sclks to read back the single self-test result. table 35. reading data from the ad7280 examples device address register address data write all 0 8-bit crc 000 32-bit write command example 1 C write 1 00000 = 5h0 011100 = 6h1c 00000000 = 8h0 1 0 00111001 = 8h39 000 32h38011c8 example 1 C write 2 00000 = 5h0 001101 = 6hd 00000000 = 8h0 1 0 01100011 = 8h63 000 32h1a01318 example 2 C write 1 00000 = 5h0 011100 = 6h1c 00000000 = 8h0 1 0 00111001 = 8h39 000 32h38011c8 example 2 C write 2 00000 = 5h0 001101 = 6hd 01010000 = 8h50 1 0 00001100 = 8hc 000 32h1aa1060 example 3 C write 1 00000 = 5h0 011100 = 6h1c 00000000 = 8h0 1 0 00111001 = 8h39 000 32h38011c8 example 3 C write 2 00000 = 5h0 001101 = 6hd 10100000 = 8ha0 1 0 10111101 = 8hbd 000 32h1b415e8 example 4 C write 1 01000 = 5h8 011100 = 6h1c 00000000 = 8h0 0 0 10111110 = 8hbe 000 32h438005f0 example 4 C write 2 00000 = 5h0 001101 = 6hd 00110000 = 8h30 1 0 10100011 = 8ha3 000 32h1a61518 example 4 C write 3 01000 = 5h8 001101 = 6hd 00000000 = 8h0 0 0 11100100 = 8he4 000 32h41a00720 example 5 C write 1 10100 = 5h14 011100 = 6h1c 00000000 = 8h0 0 0 11001011 = 8hcb 000 32ha3800658 example 5 C write 2 00000 = 5h0 001101 = 6hd 00110000 = 8h30 1 0 10100011 = 8ha3 000 32h1a61518 example 5 C write 3 10100 = 5h14 001101 = 6hd 01010000 = 8h50 0 0 11111110 = 8hfe 000 32ha1aa07f0 example 6 C write 1 11100 = 5h1c 011100 = 6h1c 00000000 = 8h0 0 0 01001110 = 8h4e 000 32he3800270 example 6 C write 2 00000 = 5h0 001101 = 6hd 00110000 = 8h30 1 0 10100011 = 8ha3 000 32h1a61518 example 6 C write 3 11100 = 5h1c 001101 = 6hd 10100000 = 8ha0 0 0 11001010 = 8hca 000 32he1b40650 example 7 C write 1 11000 = 5h18 011100 = 6h1c 00010100 = 8h14 0 0 11001011 = 8hcb 000 32hc3828658 example 7 C write 2 00000 = 5h0 001101 = 6hd 00110000 = 8h30 1 0 10100011 = 8ha3 000 32h1a61518
ad7280 preliminary technical data rev. prf | page 36 of 38 example 7 C write 3 11000 = 5h18 001101 = 6hd 10100000 = 8ha0 0 0 00011111 = 8h1f 000 32hc1b400f8 example 8 C write 1 00000 = 5h0 001110 =6he 00010101 = 8h15 1 0 11011100 = 8hdc 000 32h1c2b6e0 example 8 C write 2 00000 = 5h0 011100 = 6h1c 01010000 = 8h50 1 0 01010110 = 8h56 000 32h38a12b0 example 9 C write 1 00000 = 5h0 001101 = 6hd 00110000 = 8h30 1 0 10100011 = 8ha3 000 32h1a61518 example 9 C write 2 10000 = 5h10 001101 = 6hd 00000000 = 8h0 0 0 01000100 = 8h44 000 32h81a00220 example 9 C write 3 10000 = 5h10 011100 = 6h1c 01001100 = 8h4c 0 0 00000001 = 8h01 000 32h83898008 example 10 C write 1 00000 = 5h0 001101 = 6hd 11000000 = 8hc0 1 0 00010010 = 8h12 000 32h1b81090 example 10 C write 2 00000 = 5h0 001110 =6he 00010101 = 8h15 1 0 11011100 = 8hdc 000 32h1c2b6e0 example 10 C write 3 00000 = 5h0 011100 = 6h1c 00110000 = 8h30 1 0 11111001 = 8hf9 000 32h38617c8 example 11 C write 1 00000 = 5h0 001101 = 6hd 00110001 = 8h31 1 0 10100111 = 8ha7 000 32h1a63538 example 11 C write 2 00100 = 5h4 001101 = 6hd 11000000 = 8hc0 0 0 11000101 = 8h c5 000 32h21b80628 example 11 C write 3 00100 = 5h4 011100 = 6h1c 00110000 = 8h30 0 0 00101110 = 8h 2e 000 32h23860170
preliminary technical data ad7280 rev. prf| page 37 of 38 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 22. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters 112408-b compliant to jedec standards mo-220-wkkd. 1 0.50 bsc bottom view top view pin 1 indi c ator 7.00 bsc sq 48 13 24 25 36 37 12 exposed pad p i n 1 i n d i c a t o r 5.20 5.10 sq 5.00 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.25 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18 figure 23. 48-lead frame chip scale package [lfcsp] (cp-48-4) dimensions shown in millimeters ordering guide model temperature range package description package option ad7280wbstz 1 C40c to +85c 48-lead lqfp st-48 ad7280wdstz 1 C40c to +105c 48-lead lqfp st-48 AD7280WBCPZ 1 C40c to +85c 48-lead lfcsp cp-48-4 ad7280wdcpz 1 C40c to +105c 48-lead lfcsp cp-48-4 1 z = pb-free part.
?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr07731-0-10/09(prf) ad7280 preliminary technical data rev pre | page 38 of 38

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